drm/nva3/clk: Set PLL refclk
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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3d896d349e
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@ -163,17 +163,12 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
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}
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int
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nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
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nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
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struct nva3_clock_info *info)
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{
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struct nouveau_bios *bios = nouveau_bios(clock);
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struct nva3_clock_priv *priv = (void *)clock;
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struct nvbios_pll limits;
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u32 oclk, sclk, sdiv;
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int P, N, M, diff;
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int ret;
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u32 oclk, sclk, sdiv, diff;
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info->pll = 0;
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info->clk = 0;
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switch (khz) {
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@ -188,40 +183,64 @@ nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
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return khz;
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default:
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sclk = read_vco(priv, clk);
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sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
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/* if the clock has a PLL attached, and we can get a within
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* [-2, 3) MHz of a divider, we'll disable the PLL and use
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* the divider instead.
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*
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* divider can go as low as 2, limited here because NVIDIA
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* and the VBIOS on my NVA8 seem to prefer using the PLL
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* for 810MHz - is there a good reason?
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*/
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if (sdiv > 4) {
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sdiv = min((sclk * 2) / khz, (u32)65);
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oclk = (sclk * 2) / sdiv;
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diff = ((khz + 3000) - oclk);
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/* When imprecise, play it safe and aim for a clock lower than
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* desired rather than higher */
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if (diff < 0) {
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sdiv++;
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oclk = (sclk * 2) / sdiv;
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diff = khz - oclk;
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if (!pll || (diff >= -2000 && diff < 3000)) {
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info->clk = (((sdiv - 2) << 16) | 0x00003100);
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return oclk;
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}
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}
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if (!pll)
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return -ERANGE;
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/* divider can go as low as 2, limited here because NVIDIA
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* and the VBIOS on my NVA8 seem to prefer using the PLL
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* for 810MHz - is there a good reason?
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* XXX: PLLs with refclk 810MHz? */
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if (sdiv > 4) {
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info->clk = (((sdiv - 2) << 16) | 0x00003100);
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return oclk;
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}
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break;
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}
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return -ERANGE;
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}
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int
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nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
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struct nva3_clock_info *info)
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{
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struct nouveau_bios *bios = nouveau_bios(clock);
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struct nva3_clock_priv *priv = (void *)clock;
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int clk_khz;
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struct nvbios_pll limits;
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int P, N, M, diff;
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int ret;
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info->pll = 0;
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/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
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* PLL and use the divider instead. */
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clk_khz = nva3_clk_info(clock, clk, khz, info);
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diff = khz - clk_khz;
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if (!pll || (diff >= -2000 && diff < 3000)) {
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return clk_khz;
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}
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/* Try with PLL */
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ret = nvbios_pll_parse(bios, pll, &limits);
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if (ret)
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return ret;
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limits.refclk = read_clk(priv, clk - 0x10, true);
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if (!limits.refclk)
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clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
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if (clk_khz != limits.refclk)
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return -EINVAL;
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ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
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if (ret >= 0) {
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info->clk = nv_rd32(priv, 0x4120 + (clk * 4));
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info->pll = (P << 16) | (N << 8) | M;
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}
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@ -232,7 +251,7 @@ static int
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calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
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int clk, u32 pll, int idx)
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{
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int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx],
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int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
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&priv->eng[idx]);
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if (ret >= 0)
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return 0;
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@ -249,7 +268,7 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
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const u32 coef = pll + 4;
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if (info->pll) {
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nv_mask(priv, src0, 0x00000101, 0x00000101);
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nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
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nv_wr32(priv, coef, info->pll);
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nv_mask(priv, ctrl, 0x00000015, 0x00000015);
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nv_mask(priv, ctrl, 0x00000010, 0x00000000);
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@ -8,7 +8,7 @@ struct nva3_clock_info {
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u32 pll;
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};
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int nva3_clock_info(struct nouveau_clock *, int, u32, u32,
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int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
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struct nva3_clock_info *);
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#endif
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@ -123,7 +123,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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timing.data = 0;
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}
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ret = nva3_clock_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
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ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
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if (ret < 0) {
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nv_error(pfb, "failed mclk calculation\n");
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return ret;
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