ARM: i.MX6: Add OF configuration support for ksz9031
Adds support for ksz9031 PAD skew configuration over devicetree. Signed-off-by: Hubert Chaumette <hchaumette@adeneo-embedded.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -283,6 +283,110 @@ static int ksz9021_config_init(struct phy_device *phydev)
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return 0;
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}
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#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
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#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
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#define OP_DATA 1
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#define KSZ9031_PS_TO_REG 60
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/* Extended registers */
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#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
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#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
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#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
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#define MII_KSZ9031RN_CLK_PAD_SKEW 8
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static int ksz9031_extended_write(struct phy_device *phydev,
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u8 mode, u32 dev_addr, u32 regnum, u16 val)
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{
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
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phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
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return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
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}
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static int ksz9031_extended_read(struct phy_device *phydev,
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u8 mode, u32 dev_addr, u32 regnum)
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{
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
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phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
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phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
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return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
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}
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static int ksz9031_of_load_skew_values(struct phy_device *phydev,
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struct device_node *of_node,
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u16 reg, size_t field_sz,
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char *field[], u8 numfields)
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{
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int val[4] = {-1, -2, -3, -4};
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int matches = 0;
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u16 mask;
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u16 maxval;
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u16 newval;
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int i;
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for (i = 0; i < numfields; i++)
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if (!of_property_read_u32(of_node, field[i], val + i))
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matches++;
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if (!matches)
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return 0;
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if (matches < numfields)
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newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
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else
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newval = 0;
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maxval = (field_sz == 4) ? 0xf : 0x1f;
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for (i = 0; i < numfields; i++)
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if (val[i] != -(i + 1)) {
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mask = 0xffff;
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mask ^= maxval << (field_sz * i);
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newval = (newval & mask) |
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(((val[i] / KSZ9031_PS_TO_REG) & maxval)
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<< (field_sz * i));
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}
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return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
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}
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static int ksz9031_config_init(struct phy_device *phydev)
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{
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struct device *dev = &phydev->dev;
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struct device_node *of_node = dev->of_node;
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char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
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char *rx_data_skews[4] = {
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"rxd0-skew-ps", "rxd1-skew-ps",
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"rxd2-skew-ps", "rxd3-skew-ps"
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};
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char *tx_data_skews[4] = {
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"txd0-skew-ps", "txd1-skew-ps",
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"txd2-skew-ps", "txd3-skew-ps"
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};
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char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
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if (!of_node && dev->parent->of_node)
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of_node = dev->parent->of_node;
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if (of_node) {
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_CLK_PAD_SKEW, 5,
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clk_skews, 2);
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
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control_skews, 2);
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
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rx_data_skews, 4);
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
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tx_data_skews, 4);
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}
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return 0;
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}
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#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
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#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
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#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
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@ -469,7 +573,7 @@ static struct phy_driver ksphy_driver[] = {
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.features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
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| SUPPORTED_Asym_Pause),
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.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
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.config_init = kszphy_config_init,
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.config_init = ksz9031_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = kszphy_ack_interrupt,
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