drm/radeon: Add support for CIK GPU reset (v2)
v2: split soft reset into compute and gfx. Still need to make reset more fine grained, but this should be a start. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
8cc1a5328b
commit
6f2043ce15
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@ -27,9 +27,13 @@
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#include <linux/module.h>
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#include "drmP.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "cikd.h"
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#include "atom.h"
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extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
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/*
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* Core functions
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*/
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@ -1190,3 +1194,196 @@ static void cik_gpu_init(struct radeon_device *rdev)
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udelay(50);
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}
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/**
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* cik_gpu_is_lockup - check if the 3D engine is locked up
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Check if the 3D engine is locked up (CIK).
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* Returns true if the engine is locked, false if not.
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*/
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bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 srbm_status, srbm_status2;
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u32 grbm_status, grbm_status2;
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u32 grbm_status_se0, grbm_status_se1, grbm_status_se2, grbm_status_se3;
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srbm_status = RREG32(SRBM_STATUS);
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srbm_status2 = RREG32(SRBM_STATUS2);
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grbm_status = RREG32(GRBM_STATUS);
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grbm_status2 = RREG32(GRBM_STATUS2);
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grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
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grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
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grbm_status_se2 = RREG32(GRBM_STATUS_SE2);
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grbm_status_se3 = RREG32(GRBM_STATUS_SE3);
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if (!(grbm_status & GUI_ACTIVE)) {
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radeon_ring_lockup_update(ring);
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return false;
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}
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/* force CP activities */
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radeon_ring_force_activity(rdev, ring);
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return radeon_ring_test_lockup(rdev, ring);
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}
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/**
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* cik_gfx_gpu_soft_reset - soft reset the 3D engine and CPG
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*
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* @rdev: radeon_device pointer
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*
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* Soft reset the GFX engine and CPG blocks (CIK).
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* XXX: deal with reseting RLC and CPF
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* Returns 0 for success.
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*/
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static int cik_gfx_gpu_soft_reset(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return 0;
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dev_info(rdev->dev, "GPU GFX softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(GRBM_STATUS_SE2));
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dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(GRBM_STATUS_SE3));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(SRBM_STATUS2));
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evergreen_mc_stop(rdev, &save);
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if (radeon_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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/* reset all the gfx block and all CPG blocks */
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grbm_reset = SOFT_RESET_CPG | SOFT_RESET_GFX;
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dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
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WREG32(GRBM_SOFT_RESET, grbm_reset);
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(void)RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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(void)RREG32(GRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(GRBM_STATUS_SE2));
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dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(GRBM_STATUS_SE3));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(SRBM_STATUS2));
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evergreen_mc_resume(rdev, &save);
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return 0;
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}
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/**
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* cik_compute_gpu_soft_reset - soft reset CPC
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*
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* @rdev: radeon_device pointer
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*
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* Soft reset the CPC blocks (CIK).
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* XXX: deal with reseting RLC and CPF
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* Returns 0 for success.
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*/
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static int cik_compute_gpu_soft_reset(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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dev_info(rdev->dev, "GPU compute softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(GRBM_STATUS_SE2));
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dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(GRBM_STATUS_SE3));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(SRBM_STATUS2));
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evergreen_mc_stop(rdev, &save);
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if (radeon_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Disable CP parsing/prefetching */
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WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
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/* reset all the CPC blocks */
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grbm_reset = SOFT_RESET_CPG;
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dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
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WREG32(GRBM_SOFT_RESET, grbm_reset);
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(void)RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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(void)RREG32(GRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(GRBM_STATUS_SE2));
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dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(GRBM_STATUS_SE3));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(SRBM_STATUS2));
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evergreen_mc_resume(rdev, &save);
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return 0;
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}
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/**
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* cik_asic_reset - soft reset compute and gfx
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*
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* @rdev: radeon_device pointer
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*
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* Soft reset the CPC blocks (CIK).
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* XXX: make this more fine grained and only reset
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* what is necessary.
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* Returns 0 for success.
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*/
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int cik_asic_reset(struct radeon_device *rdev)
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{
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int r;
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r = cik_compute_gpu_soft_reset(rdev);
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if (r)
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dev_info(rdev->dev, "Compute reset failed!\n");
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return cik_gfx_gpu_soft_reset(rdev);
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}
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@ -30,6 +30,9 @@
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#define DMIF_ADDR_CALC 0xC00
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#define SRBM_STATUS2 0xE4C
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#define SRBM_STATUS 0xE50
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#define MC_SHARED_CHMAP 0x2004
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_MASK 0x0000f000
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@ -65,6 +68,83 @@
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#define GRBM_CNTL 0x8000
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#define GRBM_READ_TIMEOUT(x) ((x) << 0)
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#define GRBM_STATUS2 0x8008
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#define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
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#define ME0PIPE1_CF_RQ_PENDING (1 << 4)
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#define ME0PIPE1_PF_RQ_PENDING (1 << 5)
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#define ME1PIPE0_RQ_PENDING (1 << 6)
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#define ME1PIPE1_RQ_PENDING (1 << 7)
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#define ME1PIPE2_RQ_PENDING (1 << 8)
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#define ME1PIPE3_RQ_PENDING (1 << 9)
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#define ME2PIPE0_RQ_PENDING (1 << 10)
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#define ME2PIPE1_RQ_PENDING (1 << 11)
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#define ME2PIPE2_RQ_PENDING (1 << 12)
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#define ME2PIPE3_RQ_PENDING (1 << 13)
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#define RLC_RQ_PENDING (1 << 14)
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#define RLC_BUSY (1 << 24)
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#define TC_BUSY (1 << 25)
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#define CPF_BUSY (1 << 28)
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#define CPC_BUSY (1 << 29)
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#define CPG_BUSY (1 << 30)
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#define GRBM_STATUS 0x8010
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#define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
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#define SRBM_RQ_PENDING (1 << 5)
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#define ME0PIPE0_CF_RQ_PENDING (1 << 7)
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#define ME0PIPE0_PF_RQ_PENDING (1 << 8)
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#define GDS_DMA_RQ_PENDING (1 << 9)
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#define DB_CLEAN (1 << 12)
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#define CB_CLEAN (1 << 13)
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#define TA_BUSY (1 << 14)
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#define GDS_BUSY (1 << 15)
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#define WD_BUSY_NO_DMA (1 << 16)
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#define VGT_BUSY (1 << 17)
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#define IA_BUSY_NO_DMA (1 << 18)
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#define IA_BUSY (1 << 19)
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#define SX_BUSY (1 << 20)
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#define WD_BUSY (1 << 21)
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#define SPI_BUSY (1 << 22)
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#define BCI_BUSY (1 << 23)
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#define SC_BUSY (1 << 24)
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#define PA_BUSY (1 << 25)
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#define DB_BUSY (1 << 26)
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#define CP_COHERENCY_BUSY (1 << 28)
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#define CP_BUSY (1 << 29)
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#define CB_BUSY (1 << 30)
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#define GUI_ACTIVE (1 << 31)
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#define GRBM_STATUS_SE0 0x8014
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#define GRBM_STATUS_SE1 0x8018
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#define GRBM_STATUS_SE2 0x8038
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#define GRBM_STATUS_SE3 0x803C
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#define SE_DB_CLEAN (1 << 1)
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#define SE_CB_CLEAN (1 << 2)
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#define SE_BCI_BUSY (1 << 22)
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#define SE_VGT_BUSY (1 << 23)
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#define SE_PA_BUSY (1 << 24)
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#define SE_TA_BUSY (1 << 25)
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#define SE_SX_BUSY (1 << 26)
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#define SE_SPI_BUSY (1 << 27)
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#define SE_SC_BUSY (1 << 29)
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#define SE_DB_BUSY (1 << 30)
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#define SE_CB_BUSY (1 << 31)
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#define GRBM_SOFT_RESET 0x8020
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#define SOFT_RESET_CP (1 << 0) /* All CP blocks */
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#define SOFT_RESET_RLC (1 << 2) /* RLC */
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#define SOFT_RESET_GFX (1 << 16) /* GFX */
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#define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
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#define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
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#define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
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#define CP_MEC_CNTL 0x8234
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#define MEC_ME2_HALT (1 << 28)
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#define MEC_ME1_HALT (1 << 30)
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#define CP_ME_CNTL 0x86D8
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#define CP_CE_HALT (1 << 24)
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#define CP_PFP_HALT (1 << 26)
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#define CP_ME_HALT (1 << 28)
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#define CP_MEQ_THRESHOLDS 0x8764
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#define MEQ1_START(x) ((x) << 0)
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#define MEQ2_START(x) ((x) << 8)
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