drm/nva3/clk: HOST clock
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Roy Spliet
Ben Skeggs
parent
6a4a47cfd1
commit
70c7995d12
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@ -136,12 +136,11 @@ static int
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nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
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{
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struct nva3_clock_priv *priv = (void *)clk;
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u32 hsrc;
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switch (src) {
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case nv_clk_src_crystal:
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return nv_device(priv)->crystal;
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case nv_clk_src_href:
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return 100000;
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case nv_clk_src_core:
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return read_pll(priv, 0x00, 0x4200);
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case nv_clk_src_shader:
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@ -154,6 +153,18 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
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return read_clk(priv, 0x21, false);
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case nv_clk_src_daemon:
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return read_clk(priv, 0x25, false);
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case nv_clk_src_host:
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hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
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switch (hsrc) {
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case 0:
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return read_clk(priv, 0x1d, false);
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case 2:
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case 3:
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return 277000;
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default:
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nv_error(clk, "unknown HOST clock source %d\n", hsrc);
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return -EINVAL;
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}
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default:
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nv_error(clk, "invalid clock source %d\n", src);
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return -EINVAL;
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@ -258,6 +269,34 @@ calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
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return ret;
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}
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static int
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calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
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{
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int ret = 0;
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u32 kHz = cstate->domain[nv_clk_src_host];
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struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
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if (kHz == 277000) {
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info->clk = 0;
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info->host_out = NVA3_HOST_277;
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return 0;
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}
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info->host_out = NVA3_HOST_CLK;
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ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
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if (ret >= 0)
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return 0;
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return ret;
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}
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static void
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disable_clk_src(struct nva3_clock_priv *priv, u32 src)
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{
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nv_mask(priv, src, 0x00000100, 0x00000000);
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nv_mask(priv, src, 0x00000001, 0x00000000);
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}
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static void
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prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
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{
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@ -275,15 +314,13 @@ prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
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nv_wait(priv, ctrl, 0x00020000, 0x00020000);
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nv_mask(priv, ctrl, 0x00000010, 0x00000010);
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nv_mask(priv, ctrl, 0x00000008, 0x00000000);
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nv_mask(priv, src1, 0x00000100, 0x00000000);
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nv_mask(priv, src1, 0x00000001, 0x00000000);
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disable_clk_src(priv, src1);
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} else {
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nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
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nv_mask(priv, ctrl, 0x00000018, 0x00000018);
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udelay(20);
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nv_mask(priv, ctrl, 0x00000001, 0x00000000);
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nv_mask(priv, src0, 0x00000100, 0x00000000);
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nv_mask(priv, src0, 0x00000001, 0x00000000);
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disable_clk_src(priv, src0);
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}
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}
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@ -294,6 +331,33 @@ prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
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nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
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}
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static void
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prog_host(struct nva3_clock_priv *priv)
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{
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struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
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u32 hsrc = (nv_rd32(priv, 0xc040));
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switch (info->host_out) {
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case NVA3_HOST_277:
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if ((hsrc & 0x30000000) == 0) {
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nv_wr32(priv, 0xc040, hsrc | 0x20000000);
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disable_clk_src(priv, 0x4194);
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}
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break;
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case NVA3_HOST_CLK:
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prog_clk(priv, 0x1d, nv_clk_src_host);
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if ((hsrc & 0x30000000) >= 0x20000000) {
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nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
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}
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break;
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default:
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break;
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}
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/* This seems to be a clock gating factor on idle, always set to 64 */
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nv_wr32(priv, 0xc044, 0x3e);
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}
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static int
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nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
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{
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@ -303,7 +367,8 @@ nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
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if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
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(ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
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(ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
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(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)))
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(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
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(ret = calc_host(priv, cstate)))
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return ret;
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return 0;
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@ -317,6 +382,7 @@ nva3_clock_prog(struct nouveau_clock *clk)
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prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
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prog_clk(priv, 0x20, nv_clk_src_disp);
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prog_clk(priv, 0x21, nv_clk_src_vdec);
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prog_host(priv);
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return 0;
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}
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@ -328,12 +394,12 @@ nva3_clock_tidy(struct nouveau_clock *clk)
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static struct nouveau_clocks
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nva3_domain[] = {
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{ nv_clk_src_crystal, 0xff },
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{ nv_clk_src_href , 0xff },
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{ nv_clk_src_core , 0x00, 0, "core", 1000 },
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{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
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{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
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{ nv_clk_src_vdec , 0x03 },
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{ nv_clk_src_disp , 0x04 },
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{ nv_clk_src_host , 0x05 },
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{ nv_clk_src_max }
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};
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@ -6,6 +6,10 @@
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struct nva3_clock_info {
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u32 clk;
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u32 pll;
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enum {
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NVA3_HOST_277,
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NVA3_HOST_CLK,
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} host_out;
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};
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int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
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