drm/i915: Split PNV version of crtc_compute_clock()
Split a pnv_crtc_compute_clock(), so the differences between platforms become more obvious. With this, there are no more users of intel_limit() or the ->find_dpll() hook, so get rid of them. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-16-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -575,24 +575,6 @@ struct dpll;
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struct drm_i915_display_funcs {
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int (*get_display_clock_speed)(struct drm_device *dev);
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int (*get_fifo_size)(struct drm_device *dev, int plane);
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/**
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* find_dpll() - Find the best values for the PLL
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* @limit: limits for the PLL
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* @crtc: current CRTC
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* @target: target frequency in kHz
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* @refclk: reference clock frequency in kHz
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* @match_clock: if provided, @best_clock P divider must
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* match the P divider from @match_clock
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* used for LVDS downclocking
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* @best_clock: best PLL values found
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*
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* Returns true on success, false on failure.
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*/
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bool (*find_dpll)(const struct intel_limit *limit,
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struct intel_crtc_state *crtc_state,
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int target, int refclk,
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struct dpll *match_clock,
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struct dpll *best_clock);
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int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
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int (*compute_intermediate_wm)(struct drm_device *dev,
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struct intel_crtc *intel_crtc,
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@ -564,33 +564,6 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
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return false;
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}
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static const intel_limit_t *
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intel_limit(struct intel_crtc_state *crtc_state, int refclk)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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const intel_limit_t *limit;
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if (IS_BROXTON(dev) || IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev) ||
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HAS_PCH_SPLIT(dev) || IS_G4X(dev) || IS_GEN2(dev))
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limit = NULL;
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if (IS_PINEVIEW(dev)) {
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_pineview_lvds;
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else
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limit = &intel_limits_pineview_sdvo;
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} else if (!IS_GEN2(dev)) {
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
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limit = &intel_limits_i9xx_lvds;
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else
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limit = &intel_limits_i9xx_sdvo;
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}
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WARN_ON(limit == NULL);
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return limit;
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}
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/*
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* Platform specific helpers to calculate the port PLL loopback- (clock.m),
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* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
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@ -721,6 +694,16 @@ i9xx_select_p2_div(const intel_limit_t *limit,
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}
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}
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/*
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*
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* Target and reference clocks are specified in kHz.
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*
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* If match_clock is provided, then best_clock P divider must match the P
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* divider from @match_clock used for LVDS downclocking.
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*/
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static bool
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i9xx_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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@ -768,6 +751,16 @@ i9xx_find_best_dpll(const intel_limit_t *limit,
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return (err != target);
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}
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/*
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*
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* Target and reference clocks are specified in kHz.
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*
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* If match_clock is provided, then best_clock P divider must match the P
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* divider from @match_clock used for LVDS downclocking.
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*/
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static bool
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pnv_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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@ -817,6 +810,11 @@ pnv_find_best_dpll(const intel_limit_t *limit,
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* Returns a set of divisors for the desired target clock with the given
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*
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* Target and reference clocks are specified in kHz.
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*
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* If match_clock is provided, then best_clock P divider must match the P
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* divider from @match_clock used for LVDS downclocking.
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*/
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static bool
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g4x_find_best_dpll(const intel_limit_t *limit,
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@ -7849,43 +7847,67 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
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return 0;
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}
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static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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bool ok;
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const intel_limit_t *limit;
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int refclk = 96000;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (crtc_state->has_dsi_encoder)
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return 0;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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}
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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limit = &intel_limits_pineview_lvds;
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} else {
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limit = &intel_limits_pineview_sdvo;
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}
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if (!crtc_state->clock_set) {
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/*
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* Returns a set of divisors for the desired target clock with
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* the given refclk, or FALSE. The returned values represent
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* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
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* 2) / p1 / p2.
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*/
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limit = intel_limit(crtc_state, refclk);
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ok = dev_priv->display.find_dpll(limit, crtc_state,
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crtc_state->port_clock,
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refclk, NULL,
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&crtc_state->dpll);
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if (!ok) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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if (!crtc_state->clock_set &&
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!pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, &crtc_state->dpll)) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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i9xx_compute_dpll(crtc, crtc_state, NULL);
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return 0;
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}
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static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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const intel_limit_t *limit;
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int refclk = 96000;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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if (intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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}
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limit = &intel_limits_i9xx_lvds;
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} else {
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limit = &intel_limits_i9xx_sdvo;
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}
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if (!crtc_state->clock_set &&
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!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
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refclk, NULL, &crtc_state->dpll)) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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i9xx_compute_dpll(crtc, crtc_state, NULL);
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@ -14800,11 +14822,6 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
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*/
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void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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{
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if (IS_PINEVIEW(dev_priv))
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dev_priv->display.find_dpll = pnv_find_best_dpll;
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else
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dev_priv->display.find_dpll = i9xx_find_best_dpll;
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if (INTEL_INFO(dev_priv)->gen >= 9) {
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dev_priv->display.get_pipe_config = haswell_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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@ -14850,6 +14867,13 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else if (IS_PINEVIEW(dev_priv)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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i9xx_get_initial_plane_config;
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dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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} else if (!IS_GEN2(dev_priv)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_initial_plane_config =
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