[ARM] 4488/1: pxa: move pxa25x/pxa27x specific code out of pm.c
1. introduce a structure pxa_cpu_pm_fns for pxa25x/pxa27x specific
operations as follows:
struct pxa_cpu_pm_fns {
int save_size;
void (*save)(unsigned long *);
void (*restore)(unsigned long *);
int (*valid)(suspend_state_t state);
void (*enter)(suspend_state_t state);
}
2. processor specific registers saving and restoring are performed
by calling the corresponding (*save) and (*restore)
3. pxa_cpu_pm_fns->save_size should be initialized to the required
size for processor specific registers saving, the allocated
memory address will be passed to (*save) and (*restore)
memory allocation happens early in pxa_pm_init(), and save_size
should be assigned prior to this (which is usually true, since
pxa_pm_init() happens in device_initcall()
4. there're some redundancies for those SLEEP_SAVE_XXX and related
macros, will be fixed later, one way possible is for the system
devices to handle the specific registers saving and restoring
Signed-off-by: eric miao <eric.y.miao@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
hifive-unleashed-5.1
Eric Miao
Russell King
parent
e09d02e123
commit
711be5ccfe
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@ -24,61 +24,13 @@
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#include <asm/arch/lubbock.h>
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#include <asm/mach/time.h>
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/*
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* Debug macros
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*/
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#undef DEBUG
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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#define RESTORE_GPLEVEL(n) do { \
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GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
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GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
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} while (0)
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
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SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
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SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
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SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
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SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_ICMR,
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SLEEP_SAVE_CKEN,
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#ifdef CONFIG_PXA27x
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SLEEP_SAVE_MDREFR,
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SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
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SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
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#endif
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SLEEP_SAVE_CKSUM,
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SLEEP_SAVE_SIZE
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};
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struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
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static unsigned long *sleep_save;
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int pxa_pm_enter(suspend_state_t state)
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{
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unsigned long sleep_save[SLEEP_SAVE_SIZE];
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unsigned long checksum = 0;
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unsigned long sleep_save_checksum = 0, checksum = 0;
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int i;
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extern void pxa_cpu_pm_enter(suspend_state_t state);
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#ifdef CONFIG_IWMMXT
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/* force any iWMMXt context to ram **/
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@ -86,100 +38,35 @@ int pxa_pm_enter(suspend_state_t state)
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iwmmxt_task_disable(NULL);
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#endif
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SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
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SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
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SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
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SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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#ifdef CONFIG_PXA27x
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SAVE(MDREFR);
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SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
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SAVE(GAFR3_L); SAVE(GAFR3_U);
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SAVE(PWER); SAVE(PCFR); SAVE(PRER);
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SAVE(PFER); SAVE(PKWR);
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#endif
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SAVE(ICMR);
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ICMR = 0;
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SAVE(CKEN);
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SAVE(PSTR);
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/* Note: wake up source are set up in each machine specific files */
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/* clear GPIO transition detect bits */
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GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
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#ifdef CONFIG_PXA27x
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GEDR3 = GEDR3;
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#endif
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pxa_cpu_pm_fns->save(sleep_save);
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/* Clear sleep reset status */
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RCSR = RCSR_SMR;
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/* before sleeping, calculate and save a checksum */
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for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
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checksum += sleep_save[i];
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sleep_save[SLEEP_SAVE_CKSUM] = checksum;
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for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
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sleep_save_checksum += sleep_save[i];
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/* *** go zzz *** */
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pxa_cpu_pm_enter(state);
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pxa_cpu_pm_fns->enter(state);
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cpu_init();
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/* after sleeping, validate the checksum */
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checksum = 0;
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for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
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for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++)
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checksum += sleep_save[i];
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/* if invalid, display message and wait for a hardware reset */
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if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
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if (checksum != sleep_save_checksum) {
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#ifdef CONFIG_ARCH_LUBBOCK
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LUB_HEXLED = 0xbadbadc5;
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#endif
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while (1)
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pxa_cpu_pm_enter(state);
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pxa_cpu_pm_fns->enter(state);
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}
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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pxa_cpu_pm_fns->restore(sleep_save);
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/* restore registers */
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RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
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RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
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RESTORE(GAFR0_L); RESTORE(GAFR0_U);
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RESTORE(GAFR1_L); RESTORE(GAFR1_U);
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RESTORE(GAFR2_L); RESTORE(GAFR2_U);
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RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
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RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
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#ifdef CONFIG_PXA27x
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RESTORE(MDREFR);
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RESTORE_GPLEVEL(3); RESTORE(GPDR3);
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RESTORE(GAFR3_L); RESTORE(GAFR3_U);
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RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
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RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
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RESTORE(PFER); RESTORE(PKWR);
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#endif
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PSSR = PSSR_RDH | PSSR_PH;
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RESTORE(CKEN);
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ICLR = 0;
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ICCR = 1;
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RESTORE(ICMR);
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RESTORE(PSTR);
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#ifdef DEBUG
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printk(KERN_DEBUG "*** made it back from resume\n");
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#endif
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pr_debug("*** made it back from resume\n");
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return 0;
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}
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@ -190,3 +77,35 @@ unsigned long sleep_phys_sp(void *sp)
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{
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return virt_to_phys(sp);
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}
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static int pxa_pm_valid(suspend_state_t state)
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{
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if (pxa_cpu_pm_fns)
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return pxa_cpu_pm_fns->valid(state);
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return -EINVAL;
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}
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static struct pm_ops pxa_pm_ops = {
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.valid = pxa_pm_valid,
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.enter = pxa_pm_enter,
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};
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static int __init pxa_pm_init(void)
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{
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if (!pxa_cpu_pm_fns) {
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printk(KERN_ERR "no valid pxa_cpu_pm_fns defined\n");
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return -EINVAL;
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}
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sleep_save = kmalloc(pxa_cpu_pm_fns->save_size, GFP_KERNEL);
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if (!sleep_save) {
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printk(KERN_ERR "failed to alloc memory for pm save\n");
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return -ENOMEM;
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}
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pm_set_ops(&pxa_pm_ops);
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return 0;
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}
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device_initcall(pxa_pm_init);
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@ -110,7 +110,75 @@ EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
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#ifdef CONFIG_PM
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void pxa_cpu_pm_enter(suspend_state_t state)
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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#define RESTORE_GPLEVEL(n) do { \
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GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
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GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
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} while (0)
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
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SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
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SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
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SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
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SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_ICMR,
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SLEEP_SAVE_CKEN,
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SLEEP_SAVE_SIZE
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};
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static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
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SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
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SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
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SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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SAVE(ICMR);
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SAVE(CKEN);
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SAVE(PSTR);
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}
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static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
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{
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/* restore registers */
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RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
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RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
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RESTORE(GAFR0_L); RESTORE(GAFR0_U);
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RESTORE(GAFR1_L); RESTORE(GAFR1_U);
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RESTORE(GAFR2_L); RESTORE(GAFR2_U);
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RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
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RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
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RESTORE(CKEN);
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RESTORE(ICMR);
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RESTORE(PSTR);
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}
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static void pxa25x_cpu_pm_enter(suspend_state_t state)
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{
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extern void pxa_cpu_suspend(unsigned int);
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extern void pxa_cpu_resume(void);
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@ -126,10 +194,18 @@ void pxa_cpu_pm_enter(suspend_state_t state)
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}
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}
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static struct pm_ops pxa25x_pm_ops = {
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.enter = pxa_pm_enter,
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static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
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.save_size = SLEEP_SAVE_SIZE,
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.valid = pm_valid_only_mem,
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.save = pxa25x_cpu_pm_save,
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.restore = pxa25x_cpu_pm_restore,
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.enter = pxa25x_cpu_pm_enter,
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};
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static void __init pxa25x_init_pm(void)
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{
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pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
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}
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#endif
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void __init pxa25x_init_irq(void)
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@ -159,7 +235,7 @@ static int __init pxa25x_init(void)
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if ((ret = pxa_init_dma(16)))
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return ret;
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#ifdef CONFIG_PM
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pm_set_ops(&pxa25x_pm_ops);
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pxa25x_init_pm();
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#endif
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ret = platform_add_devices(pxa25x_devices,
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ARRAY_SIZE(pxa25x_devices));
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@ -126,14 +126,109 @@ EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
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#ifdef CONFIG_PM
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void pxa_cpu_pm_enter(suspend_state_t state)
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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#define RESTORE_GPLEVEL(n) do { \
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GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
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GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
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} while (0)
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
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SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
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SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
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SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
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SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_ICMR,
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SLEEP_SAVE_CKEN,
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SLEEP_SAVE_MDREFR,
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SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
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SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
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SLEEP_SAVE_SIZE
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};
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void pxa27x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
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SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
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SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
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SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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SAVE(GAFR3_L); SAVE(GAFR3_U);
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SAVE(MDREFR);
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SAVE(PWER); SAVE(PCFR); SAVE(PRER);
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SAVE(PFER); SAVE(PKWR);
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SAVE(ICMR); ICMR = 0;
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SAVE(CKEN);
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SAVE(PSTR);
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/* Clear GPIO transition detect bits */
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GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
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}
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void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
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{
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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/* restore registers */
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RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
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RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
|
||||
RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
|
||||
RESTORE(GAFR0_L); RESTORE(GAFR0_U);
|
||||
RESTORE(GAFR1_L); RESTORE(GAFR1_U);
|
||||
RESTORE(GAFR2_L); RESTORE(GAFR2_U);
|
||||
RESTORE(GAFR3_L); RESTORE(GAFR3_U);
|
||||
RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
|
||||
RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
|
||||
RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
|
||||
|
||||
RESTORE(MDREFR);
|
||||
RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
|
||||
RESTORE(PFER); RESTORE(PKWR);
|
||||
|
||||
PSSR = PSSR_RDH | PSSR_PH;
|
||||
|
||||
RESTORE(CKEN);
|
||||
|
||||
ICLR = 0;
|
||||
ICCR = 1;
|
||||
RESTORE(ICMR);
|
||||
RESTORE(PSTR);
|
||||
}
|
||||
|
||||
void pxa27x_cpu_pm_enter(suspend_state_t state)
|
||||
{
|
||||
extern void pxa_cpu_standby(void);
|
||||
extern void pxa_cpu_suspend(unsigned int);
|
||||
extern void pxa_cpu_resume(void);
|
||||
|
||||
if (state == PM_SUSPEND_STANDBY)
|
||||
CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) | (1 << CKEN_LCD) | (1 << CKEN_PWM0);
|
||||
CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
|
||||
(1 << CKEN_LCD) | (1 << CKEN_PWM0);
|
||||
else
|
||||
CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
|
||||
|
||||
|
|
@ -155,15 +250,23 @@ void pxa_cpu_pm_enter(suspend_state_t state)
|
|||
}
|
||||
}
|
||||
|
||||
static int pxa27x_pm_valid(suspend_state_t state)
|
||||
static int pxa27x_cpu_pm_valid(suspend_state_t state)
|
||||
{
|
||||
return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
|
||||
}
|
||||
|
||||
static struct pm_ops pxa27x_pm_ops = {
|
||||
.enter = pxa_pm_enter,
|
||||
.valid = pxa27x_pm_valid,
|
||||
static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
|
||||
.save_size = SLEEP_SAVE_SIZE,
|
||||
.save = pxa27x_cpu_pm_save,
|
||||
.restore = pxa27x_cpu_pm_restore,
|
||||
.valid = pxa27x_cpu_pm_valid,
|
||||
.enter = pxa27x_cpu_pm_enter,
|
||||
};
|
||||
|
||||
static void __init pxa27x_init_pm(void)
|
||||
{
|
||||
pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -249,7 +352,7 @@ static int __init pxa27x_init(void)
|
|||
if ((ret = pxa_init_dma(32)))
|
||||
return ret;
|
||||
#ifdef CONFIG_PM
|
||||
pm_set_ops(&pxa27x_pm_ops);
|
||||
pxa27x_init_pm();
|
||||
#endif
|
||||
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,5 +7,14 @@
|
|||
*
|
||||
*/
|
||||
|
||||
extern int pxa_pm_prepare(suspend_state_t state);
|
||||
struct pxa_cpu_pm_fns {
|
||||
int save_size;
|
||||
void (*save)(unsigned long *);
|
||||
void (*restore)(unsigned long *);
|
||||
int (*valid)(suspend_state_t state);
|
||||
void (*enter)(suspend_state_t state);
|
||||
};
|
||||
|
||||
extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
|
||||
|
||||
extern int pxa_pm_enter(suspend_state_t state);
|
||||
|
|
|
|||
Loading…
Reference in New Issue