![Eric Miao](/assets/img/avatar_default.png)
1. introduce a structure pxa_cpu_pm_fns for pxa25x/pxa27x specific operations as follows: struct pxa_cpu_pm_fns { int save_size; void (*save)(unsigned long *); void (*restore)(unsigned long *); int (*valid)(suspend_state_t state); void (*enter)(suspend_state_t state); } 2. processor specific registers saving and restoring are performed by calling the corresponding (*save) and (*restore) 3. pxa_cpu_pm_fns->save_size should be initialized to the required size for processor specific registers saving, the allocated memory address will be passed to (*save) and (*restore) memory allocation happens early in pxa_pm_init(), and save_size should be assigned prior to this (which is usually true, since pxa_pm_init() happens in device_initcall() 4. there're some redundancies for those SLEEP_SAVE_XXX and related macros, will be fixed later, one way possible is for the system devices to handle the specific registers saving and restoring Signed-off-by: eric miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
251 lines
6 KiB
C
251 lines
6 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa25x.c
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* Code specific to PXA21x/25x/26x variants.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Since this file should be linked before any other machine specific file,
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* the __initcall() here will be executed first. This serves as default
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* initialization stuff for PXA machines which can be overridden later if
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* need be.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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#include "generic.h"
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#include "devices.h"
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/*
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* Various clock factors driven by the CCCR register.
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*/
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/* Crystal Frequency to Memory Frequency Multiplier (L) */
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static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
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/* Memory Frequency to Run Mode Frequency Multiplier (M) */
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static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
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/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
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/* Note: we store the value N * 2 here. */
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static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
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/* Crystal clock */
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#define BASE_CLK 3686400
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/*
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* Get the clock frequency as reflected by CCCR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int get_clk_frequency_khz(int info)
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{
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unsigned long cccr, turbo;
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unsigned int l, L, m, M, n2, N;
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cccr = CCCR;
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
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l = L_clk_mult[(cccr >> 0) & 0x1f];
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m = M_clk_mult[(cccr >> 5) & 0x03];
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n2 = N2_clk_mult[(cccr >> 7) & 0x07];
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L = l * BASE_CLK;
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M = m * L;
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N = n2 * M / 2;
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if(info)
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{
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L += 5000;
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printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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M += 5000;
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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N += 5000;
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
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(turbo & 1) ? "" : "in" );
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}
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return (turbo & 1) ? (N/1000) : (M/1000);
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}
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EXPORT_SYMBOL(get_clk_frequency_khz);
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/*
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* Return the current memory clock frequency in units of 10kHz
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*/
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unsigned int get_memclk_frequency_10khz(void)
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{
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return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
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}
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EXPORT_SYMBOL(get_memclk_frequency_10khz);
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/*
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* Return the current LCD clock frequency in units of 10kHz
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*/
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unsigned int get_lcdclk_frequency_10khz(void)
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{
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return get_memclk_frequency_10khz();
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}
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EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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#define RESTORE_GPLEVEL(n) do { \
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GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
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GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
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} while (0)
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_START = 0,
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SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
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SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
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SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
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SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
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SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_ICMR,
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SLEEP_SAVE_CKEN,
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SLEEP_SAVE_SIZE
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};
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static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
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SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
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SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
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SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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SAVE(ICMR);
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SAVE(CKEN);
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SAVE(PSTR);
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}
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static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
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{
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/* restore registers */
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RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
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RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
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RESTORE(GAFR0_L); RESTORE(GAFR0_U);
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RESTORE(GAFR1_L); RESTORE(GAFR1_U);
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RESTORE(GAFR2_L); RESTORE(GAFR2_U);
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RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
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RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
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RESTORE(CKEN);
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RESTORE(ICMR);
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RESTORE(PSTR);
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}
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static void pxa25x_cpu_pm_enter(suspend_state_t state)
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{
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extern void pxa_cpu_suspend(unsigned int);
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extern void pxa_cpu_resume(void);
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CKEN = 0;
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switch (state) {
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa_cpu_suspend(PWRMODE_SLEEP);
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break;
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}
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}
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static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
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.save_size = SLEEP_SAVE_SIZE,
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.valid = pm_valid_only_mem,
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.save = pxa25x_cpu_pm_save,
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.restore = pxa25x_cpu_pm_restore,
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.enter = pxa25x_cpu_pm_enter,
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};
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static void __init pxa25x_init_pm(void)
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{
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pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
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}
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#endif
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void __init pxa25x_init_irq(void)
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{
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pxa_init_irq_low();
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pxa_init_irq_gpio(85);
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}
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static struct platform_device *pxa25x_devices[] __initdata = {
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&pxa_device_mci,
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&pxa_device_udc,
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&pxa_device_fb,
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&pxa_device_ffuart,
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&pxa_device_btuart,
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&pxa_device_stuart,
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&pxa_device_i2c,
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&pxa_device_i2s,
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&pxa_device_ficp,
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&pxa_device_rtc,
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};
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static int __init pxa25x_init(void)
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{
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int ret = 0;
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if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
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if ((ret = pxa_init_dma(16)))
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return ret;
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#ifdef CONFIG_PM
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pxa25x_init_pm();
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#endif
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ret = platform_add_devices(pxa25x_devices,
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ARRAY_SIZE(pxa25x_devices));
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}
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/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
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if (cpu_is_pxa25x())
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ret = platform_device_register(&pxa_device_hwuart);
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return ret;
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}
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subsys_initcall(pxa25x_init);
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