drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds
Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-2-chris@chris-wilson.co.uk
(cherry picked from commit 19f1f627b3
)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
parent
ef50fa9bd1
commit
7237b190ad
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@ -692,6 +692,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
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return 0;
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}
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static void
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ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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/* WaDisableEarlyCull:ivb */
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wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
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/* WaDisablePSDDualDispatchEnable:ivb */
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if (IS_IVB_GT1(i915))
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wa_masked_en(wal,
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GEN7_HALF_SLICE_CHICKEN1,
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GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
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/* WaDisable_RenderCache_OperationalFlush:ivb */
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wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
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/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
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wa_masked_dis(wal,
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GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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/* WaApplyL3ControlAndL3ChickenMode:ivb */
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wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
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wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
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/* WaForceL3Serialization:ivb */
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wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
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/*
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* WaVSThreadDispatchOverride:ivb,vlv
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*
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* This actually overrides the dispatch
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* mode for all thread types.
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*/
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wa_write_masked_or(wal, GEN7_FF_THREAD_MODE,
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GEN7_FF_SCHED_MASK,
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GEN7_FF_TS_SCHED_HW |
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GEN7_FF_VS_SCHED_HW |
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GEN7_FF_DS_SCHED_HW);
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if (0) { /* causes HiZ corruption on ivb:gt1 */
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/* enable HiZ Raw Stall Optimization */
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wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
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}
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/* WaDisable4x2SubspanOptimization:ivb */
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wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
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/*
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* BSpec recommends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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wa_add(wal, GEN7_GT_MODE, 0,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4),
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GEN6_WIZ_HASHING_16x4);
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}
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static void
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hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
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{
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@ -1011,6 +1071,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
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skl_gt_workarounds_init(i915, wal);
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else if (IS_HASWELL(i915))
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hsw_gt_workarounds_init(i915, wal);
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else if (IS_IVYBRIDGE(i915))
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ivb_gt_workarounds_init(i915, wal);
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else if (INTEL_GEN(i915) <= 8)
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return;
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else
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@ -7896,7 +7896,7 @@ enum {
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/* GEN7 chicken */
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#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
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#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
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#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
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#define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
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#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
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@ -7247,32 +7247,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
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I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
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/* WaDisableEarlyCull:ivb */
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I915_WRITE(_3D_CHICKEN3,
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_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
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/* WaDisableBackToBackFlipFix:ivb */
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I915_WRITE(IVB_CHICKEN3,
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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/* WaDisablePSDDualDispatchEnable:ivb */
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if (IS_IVB_GT1(dev_priv))
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I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
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_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
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/* WaDisable_RenderCache_OperationalFlush:ivb */
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I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
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/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
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I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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/* WaApplyL3ControlAndL3ChickenMode:ivb */
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I915_WRITE(GEN7_L3CNTLREG1,
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GEN7_WA_FOR_GEN7_L3_CONTROL);
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I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
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GEN7_WA_L3_CHICKEN_MODE);
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if (IS_IVB_GT1(dev_priv))
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I915_WRITE(GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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@ -7284,10 +7263,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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}
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/* WaForceL3Serialization:ivb */
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I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
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~L3SQ_URB_READ_CAM_MATCH_DISABLE);
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/*
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* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
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* This implements the WaDisableRCZUnitClockGating:ivb workaround.
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@ -7302,29 +7277,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
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g4x_disable_trickle_feed(dev_priv);
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gen7_setup_fixed_func_scheduler(dev_priv);
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if (0) { /* causes HiZ corruption on ivb:gt1 */
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/* enable HiZ Raw Stall Optimization */
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I915_WRITE(CACHE_MODE_0_GEN7,
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_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
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}
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/* WaDisable4x2SubspanOptimization:ivb */
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I915_WRITE(CACHE_MODE_1,
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_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
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/*
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* BSpec recommends 8x4 when MSAA is used,
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* however in practice 16x4 seems fastest.
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*
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* Note that PS/WM thread counts depend on the WIZ hashing
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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I915_WRITE(GEN7_GT_MODE,
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_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
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snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
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snpcr &= ~GEN6_MBC_SNPCR_MASK;
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snpcr |= GEN6_MBC_SNPCR_MED;
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