powerpc/eeh: EEH backend for P7IOC
For EEH on PowerNV platform, the overall architecture is different from that on pSeries platform. In order to support multiple I/O chips in future, we split EEH to 3 layers for PowerNV platform: EEH core, platform layer, I/O layer. It would give EEH implementation on PowerNV platform much more flexibility in future. The patch adds the EEH backend for P7IOC. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -3,3 +3,4 @@ obj-y += opal-rtc.o opal-nvram.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_PCI) += pci.o pci-p5ioc2.o pci-ioda.o
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obj-$(CONFIG_EEH) += eeh-ioda.o
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45
arch/powerpc/platforms/powernv/eeh-ioda.c
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45
arch/powerpc/platforms/powernv/eeh-ioda.c
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/*
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* The file intends to implement the functions needed by EEH, which is
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* built on IODA compliant chip. Actually, lots of functions related
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* to EEH would be built based on the OPAL APIs.
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*
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* Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/bootmem.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <asm/eeh.h>
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#include <asm/eeh_event.h>
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#include <asm/io.h>
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#include <asm/iommu.h>
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#include <asm/msi_bitmap.h>
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#include <asm/opal.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include <asm/tce.h>
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#include "powernv.h"
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#include "pci.h"
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struct pnv_eeh_ops ioda_eeh_ops = {
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.post_init = NULL,
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.set_option = NULL,
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.get_state = NULL,
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.reset = NULL,
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.get_log = NULL,
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.configure_bridge = NULL,
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.next_error = NULL
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};
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@ -66,15 +66,35 @@ struct pnv_ioda_pe {
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struct list_head list;
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};
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/* IOC dependent EEH operations */
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#ifdef CONFIG_EEH
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struct pnv_eeh_ops {
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int (*post_init)(struct pci_controller *hose);
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int (*set_option)(struct eeh_pe *pe, int option);
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int (*get_state)(struct eeh_pe *pe);
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int (*reset)(struct eeh_pe *pe, int option);
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int (*get_log)(struct eeh_pe *pe, int severity,
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char *drv_log, unsigned long len);
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int (*configure_bridge)(struct eeh_pe *pe);
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int (*next_error)(struct eeh_pe **pe);
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};
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#endif /* CONFIG_EEH */
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struct pnv_phb {
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struct pci_controller *hose;
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enum pnv_phb_type type;
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enum pnv_phb_model model;
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u64 hub_id;
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u64 opal_id;
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void __iomem *regs;
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int initialized;
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spinlock_t lock;
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#ifdef CONFIG_EEH
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struct pnv_eeh_ops *eeh_ops;
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int eeh_enabled;
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#endif
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#ifdef CONFIG_PCI_MSI
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unsigned int msi_base;
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unsigned int msi32_support;
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@ -150,6 +170,9 @@ struct pnv_phb {
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};
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extern struct pci_ops pnv_pci_ops;
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#ifdef CONFIG_EEH
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extern struct pnv_eeh_ops ioda_eeh_ops;
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#endif
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extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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