selftests/powerpc: entry flush test
Add a test modelled on the RFI flush test which counts the number of L1D misses doing a simple syscall with the entry flush on and off. For simplicity of backporting, this test duplicates a lot of code from rfi_flush. We clean that up in the next patch. Signed-off-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>zero-sugar-mainline-defconfig
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# SPDX-License-Identifier: GPL-2.0-only
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rfi_flush
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rfi_flush
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entry_flush
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# SPDX-License-Identifier: GPL-2.0+
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# SPDX-License-Identifier: GPL-2.0+
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TEST_GEN_PROGS := rfi_flush spectre_v2
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TEST_GEN_PROGS := rfi_flush entry_flush spectre_v2
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top_srcdir = ../../../../..
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top_srcdir = ../../../../..
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CFLAGS += -I../../../../../usr/include
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CFLAGS += -I../../../../../usr/include
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@ -0,0 +1,198 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 IBM Corporation.
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*/
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#define __SANE_USERSPACE_TYPES__
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#include <sys/types.h>
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#include <stdint.h>
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#include <malloc.h>
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#include <unistd.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdio.h>
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#include "utils.h"
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#define CACHELINE_SIZE 128
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struct perf_event_read {
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__u64 nr;
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__u64 l1d_misses;
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};
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static inline __u64 load(void *addr)
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{
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__u64 tmp;
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asm volatile("ld %0,0(%1)" : "=r"(tmp) : "b"(addr));
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return tmp;
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}
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static void syscall_loop(char *p, unsigned long iterations,
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unsigned long zero_size)
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{
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for (unsigned long i = 0; i < iterations; i++) {
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for (unsigned long j = 0; j < zero_size; j += CACHELINE_SIZE)
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load(p + j);
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getppid();
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}
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}
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static void sigill_handler(int signr, siginfo_t *info, void *unused)
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{
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static int warned;
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ucontext_t *ctx = (ucontext_t *)unused;
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unsigned long *pc = &UCONTEXT_NIA(ctx);
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/* mtspr 3,RS to check for move to DSCR below */
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if ((*((unsigned int *)*pc) & 0xfc1fffff) == 0x7c0303a6) {
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if (!warned++)
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printf("WARNING: Skipping over dscr setup. Consider running 'ppc64_cpu --dscr=1' manually.\n");
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*pc += 4;
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} else {
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printf("SIGILL at %p\n", pc);
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abort();
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}
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}
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static void set_dscr(unsigned long val)
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{
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static int init;
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struct sigaction sa;
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if (!init) {
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memset(&sa, 0, sizeof(sa));
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sa.sa_sigaction = sigill_handler;
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sa.sa_flags = SA_SIGINFO;
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if (sigaction(SIGILL, &sa, NULL))
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perror("sigill_handler");
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init = 1;
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}
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asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR));
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}
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int entry_flush_test(void)
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{
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char *p;
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int repetitions = 10;
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int fd, passes = 0, iter, rc = 0;
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struct perf_event_read v;
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__u64 l1d_misses_total = 0;
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unsigned long iterations = 100000, zero_size = 24 * 1024;
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unsigned long l1d_misses_expected;
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int rfi_flush_orig;
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int entry_flush, entry_flush_orig;
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SKIP_IF(geteuid() != 0);
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// The PMU event we use only works on Power7 or later
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SKIP_IF(!have_hwcap(PPC_FEATURE_ARCH_2_06));
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if (read_debugfs_file("powerpc/rfi_flush", &rfi_flush_orig) < 0) {
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perror("Unable to read powerpc/rfi_flush debugfs file");
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SKIP_IF(1);
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}
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if (read_debugfs_file("powerpc/entry_flush", &entry_flush_orig) < 0) {
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perror("Unable to read powerpc/entry_flush debugfs file");
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SKIP_IF(1);
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}
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if (rfi_flush_orig != 0) {
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if (write_debugfs_file("powerpc/rfi_flush", 0) < 0) {
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perror("error writing to powerpc/rfi_flush debugfs file");
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FAIL_IF(1);
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}
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}
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entry_flush = entry_flush_orig;
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fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1);
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FAIL_IF(fd < 0);
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p = (char *)memalign(zero_size, CACHELINE_SIZE);
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FAIL_IF(perf_event_enable(fd));
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// disable L1 prefetching
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set_dscr(1);
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iter = repetitions;
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/*
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* We expect to see l1d miss for each cacheline access when entry_flush
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* is set. Allow a small variation on this.
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*/
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l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2);
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again:
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FAIL_IF(perf_event_reset(fd));
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syscall_loop(p, iterations, zero_size);
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FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v));
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if (entry_flush && v.l1d_misses >= l1d_misses_expected)
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passes++;
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else if (!entry_flush && v.l1d_misses < (l1d_misses_expected / 2))
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passes++;
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l1d_misses_total += v.l1d_misses;
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while (--iter)
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goto again;
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if (passes < repetitions) {
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printf("FAIL (L1D misses with entry_flush=%d: %llu %c %lu) [%d/%d failures]\n",
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entry_flush, l1d_misses_total, entry_flush ? '<' : '>',
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entry_flush ? repetitions * l1d_misses_expected :
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repetitions * l1d_misses_expected / 2,
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repetitions - passes, repetitions);
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rc = 1;
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} else {
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printf("PASS (L1D misses with entry_flush=%d: %llu %c %lu) [%d/%d pass]\n",
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entry_flush, l1d_misses_total, entry_flush ? '>' : '<',
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entry_flush ? repetitions * l1d_misses_expected :
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repetitions * l1d_misses_expected / 2,
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passes, repetitions);
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}
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if (entry_flush == entry_flush_orig) {
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entry_flush = !entry_flush_orig;
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if (write_debugfs_file("powerpc/entry_flush", entry_flush) < 0) {
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perror("error writing to powerpc/entry_flush debugfs file");
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return 1;
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}
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iter = repetitions;
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l1d_misses_total = 0;
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passes = 0;
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goto again;
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}
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perf_event_disable(fd);
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close(fd);
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set_dscr(0);
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if (write_debugfs_file("powerpc/rfi_flush", rfi_flush_orig) < 0) {
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perror("unable to restore original value of powerpc/rfi_flush debugfs file");
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return 1;
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}
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if (write_debugfs_file("powerpc/entry_flush", entry_flush_orig) < 0) {
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perror("unable to restore original value of powerpc/entry_flush debugfs file");
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return 1;
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}
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return rc;
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}
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int main(int argc, char *argv[])
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{
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return test_harness(entry_flush_test, "entry_flush_test");
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}
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