IB/ipath: Remove incompletely implemented ipath_runtime flags and code
The IPATH_RUNTIME_PBC_REWRITE and the IPATH_RUNTIME_LOOSE_DMA_ALIGN flags were not ever implemented correctly and did not turn out to be necessary. Remove the last vestiges of these flags but mark the spot with a comment to remind us to not reuse these flags in the interest of binary compatibility. The INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR bit was also not found to be useful, so it was dropped in the cleanup as well. Signed-off-by: John Gregor <john.gregor@qlogic.com> Signed-off-by: Arthur Jones <arthur.jones@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -189,8 +189,7 @@ typedef enum _ipath_ureg {
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#define IPATH_RUNTIME_FORCE_WC_ORDER 0x4
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#define IPATH_RUNTIME_RCVHDR_COPY 0x8
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#define IPATH_RUNTIME_MASTER 0x10
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#define IPATH_RUNTIME_PBC_REWRITE 0x20
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#define IPATH_RUNTIME_LOOSE_DMA_ALIGN 0x40
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/* 0x20 and 0x40 are no longer used, but are reserved for ABI compatibility */
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/*
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* This structure is returned by ipath_userinit() immediately after
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@ -296,13 +296,6 @@ static const struct ipath_cregs ipath_pe_cregs = {
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#define IPATH_GPIO_SCL (1ULL << \
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(_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
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/*
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* Rev2 silicon allows suppressing check for ArmLaunch errors.
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* this can speed up short packet sends on systems that do
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* not guaranteee write-order.
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*/
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#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
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/* 6120 specific hardware errors... */
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static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
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INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
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@ -680,17 +673,6 @@ static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
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val |= dd->ipath_rx_pol_inv <<
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INFINIPATH_XGXS_RX_POL_SHIFT;
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}
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if (dd->ipath_minrev >= 2) {
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/* Rev 2. can tolerate multiple writes to PBC, and
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* allowing them can provide lower latency on some
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* CPUs, but this feature is off by default, only
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* turned on by setting D63 of XGXSconfig reg.
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* May want to make this conditional more
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* fine-grained in future. This is not exactly
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* related to XGXS, but where the bit ended up.
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*/
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val |= INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR;
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}
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if (val != prev_val)
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ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
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@ -1324,13 +1306,6 @@ static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
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dd = pd->port_dd;
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if (dd != NULL && dd->ipath_minrev >= 2) {
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ipath_cdbg(PROC, "IBA6120 Rev2, allow multiple PBC write\n");
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kinfo->spi_runtime_flags |= IPATH_RUNTIME_PBC_REWRITE;
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ipath_cdbg(PROC, "IBA6120 Rev2, allow loose DMA alignment\n");
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kinfo->spi_runtime_flags |= IPATH_RUNTIME_LOOSE_DMA_ALIGN;
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}
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done:
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kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
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return 0;
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