drm/i915: Wait for vblank in i9xx_disable_crtc() for gen 2 only
The wait for other gens was added in commit564ed191f5
("drm/i915: gmch: fix stuck primary plane due to memory self-refresh mode") since that's necessary when disabling cxsr. However, cxsr disabling was later moved to intel_pre_disable_primary() in commit87d4300a7d
("drm/i915: Move intel_(pre_disable/post_enable)_primary to intel_display.c, and use it there.") and that function got its own vblank wait for cxsr in commit262cd2e154
("drm/i915: CHV DDR DVFS support and another watermark rewrite"). So remove the extra vblank wait from i9xx_crtc_distable(). Cc: Kalyan Kondapally <kalyan.kondapally@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1458634284-6080-1-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -6212,10 +6212,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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/*
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* On gen2 planes are double buffered but the pipe isn't, so we must
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* wait for planes to fully turn off before disabling the pipe.
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* We also need to wait on all gmch platforms because of the
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* self-refresh mode constraint explained above.
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*/
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intel_wait_for_vblank(dev, pipe);
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if (IS_GEN2(dev))
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intel_wait_for_vblank(dev, pipe);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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encoder->disable(encoder);
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