drm/radeon: add timeout argument to radeon_fence_wait_seq v2
This makes it possible to wait for a specific amount of time, rather than wait until infinity. v2 (chk): rebased on other changes Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -364,28 +364,31 @@ static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
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}
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/**
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* radeon_fence_wait_seq - wait for a specific sequence numbers
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* radeon_fence_wait_seq_timeout - wait for a specific sequence numbers
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*
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* @rdev: radeon device pointer
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* @target_seq: sequence number(s) we want to wait for
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* @intr: use interruptable sleep
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* @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
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*
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* Wait for the requested sequence number(s) to be written by any ring
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* (all asics). Sequnce number array is indexed by ring id.
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* @intr selects whether to use interruptable (true) or non-interruptable
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* (false) sleep when waiting for the sequence number. Helper function
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* for radeon_fence_wait_*().
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* Returns 0 if the sequence number has passed, error for all other cases.
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* Returns remaining time if the sequence number has passed, 0 when
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* the wait timeout, or an error for all other cases.
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* -EDEADLK is returned when a GPU lockup has been detected.
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*/
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static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
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bool intr)
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static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
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u64 *target_seq, bool intr,
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long timeout)
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{
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long r;
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int i;
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if (radeon_fence_any_seq_signaled(rdev, target_seq))
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return 0;
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return timeout;
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/* enable IRQs and tracing */
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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@ -399,11 +402,11 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
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if (intr) {
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r = wait_event_interruptible_timeout(rdev->fence_queue, (
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radeon_fence_any_seq_signaled(rdev, target_seq)
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|| rdev->needs_reset), MAX_SCHEDULE_TIMEOUT);
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|| rdev->needs_reset), timeout);
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} else {
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r = wait_event_timeout(rdev->fence_queue, (
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radeon_fence_any_seq_signaled(rdev, target_seq)
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|| rdev->needs_reset), MAX_SCHEDULE_TIMEOUT);
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|| rdev->needs_reset), timeout);
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}
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if (rdev->needs_reset)
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@ -417,14 +420,14 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
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trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
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}
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return r < 0 ? r : 0;
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return r;
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}
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/**
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* radeon_fence_wait - wait for a fence to signal
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*
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* @fence: radeon fence object
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* @intr: use interruptable sleep
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* @intr: use interruptible sleep
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*
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* Wait for the requested fence to signal (all asics).
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* @intr selects whether to use interruptable (true) or non-interruptable
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@ -434,7 +437,7 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
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int radeon_fence_wait(struct radeon_fence *fence, bool intr)
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{
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uint64_t seq[RADEON_NUM_RINGS] = {};
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int r;
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long r;
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if (fence == NULL) {
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WARN(1, "Querying an invalid fence : %p !\n", fence);
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@ -445,9 +448,10 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr)
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if (seq[fence->ring] == RADEON_FENCE_SIGNALED_SEQ)
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return 0;
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r = radeon_fence_wait_seq(fence->rdev, seq, intr);
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if (r)
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r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
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if (r < 0) {
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return r;
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}
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fence->seq = RADEON_FENCE_SIGNALED_SEQ;
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return 0;
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@ -472,7 +476,7 @@ int radeon_fence_wait_any(struct radeon_device *rdev,
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{
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uint64_t seq[RADEON_NUM_RINGS];
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unsigned i, num_rings = 0;
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int r;
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long r;
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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seq[i] = 0;
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@ -493,8 +497,8 @@ int radeon_fence_wait_any(struct radeon_device *rdev,
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if (num_rings == 0)
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return -ENOENT;
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r = radeon_fence_wait_seq(rdev, seq, intr);
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if (r) {
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r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
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if (r < 0) {
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return r;
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}
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return 0;
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@ -513,6 +517,7 @@ int radeon_fence_wait_any(struct radeon_device *rdev,
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int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
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{
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uint64_t seq[RADEON_NUM_RINGS] = {};
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long r;
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seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
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if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
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@ -520,7 +525,10 @@ int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
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already the last emited fence */
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return -ENOENT;
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}
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return radeon_fence_wait_seq(rdev, seq, false);
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r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
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if (r < 0)
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return r;
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return 0;
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}
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/**
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@ -536,18 +544,18 @@ int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
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int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)
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{
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uint64_t seq[RADEON_NUM_RINGS] = {};
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int r;
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long r;
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seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
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if (!seq[ring])
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return 0;
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r = radeon_fence_wait_seq(rdev, seq, false);
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if (r) {
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r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
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if (r < 0) {
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if (r == -EDEADLK)
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return -EDEADLK;
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dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%d)\n",
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dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
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ring, r);
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}
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return 0;
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