drm/radeon: update ib_execute for SI (v2)
When submitting a CONST_IB, emit a SWITCH_BUFFER packet before the CONST_IB. This isn't strictly necessary (the driver will work fine without it), but is good practice and allows for more flexible DE/CE sychronization options in the future. Current userspace drivers do not take advantage of the CE yet. v2: - clean up code flow a bit - no need to flush caches for CONST IB Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -1765,18 +1765,23 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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u32 header;
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if (ring->rptr_save_reg) {
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uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, ((ring->rptr_save_reg -
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PACKET3_SET_CONFIG_REG_START) >> 2));
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radeon_ring_write(ring, next_rptr);
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}
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if (ib->is_const_ib) {
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/* set switch buffer packet before const IB */
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radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
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radeon_ring_write(ring, 0);
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if (ib->is_const_ib)
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header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
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else
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} else {
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if (ring->rptr_save_reg) {
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uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, ((ring->rptr_save_reg -
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PACKET3_SET_CONFIG_REG_START) >> 2));
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radeon_ring_write(ring, next_rptr);
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}
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header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
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}
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radeon_ring_write(ring, header);
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radeon_ring_write(ring,
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@ -1787,18 +1792,20 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
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radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
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/* flush read cache over gart for this vmid */
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
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radeon_ring_write(ring, ib->vm_id);
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
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PACKET3_TC_ACTION_ENA |
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PACKET3_SH_KCACHE_ACTION_ENA |
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PACKET3_SH_ICACHE_ACTION_ENA);
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radeon_ring_write(ring, 0xFFFFFFFF);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 10); /* poll interval */
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if (!ib->is_const_ib) {
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/* flush read cache over gart for this vmid */
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
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radeon_ring_write(ring, ib->vm_id);
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
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PACKET3_TC_ACTION_ENA |
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PACKET3_SH_KCACHE_ACTION_ENA |
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PACKET3_SH_ICACHE_ACTION_ENA);
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radeon_ring_write(ring, 0xFFFFFFFF);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 10); /* poll interval */
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}
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}
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/*
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@ -901,5 +901,6 @@
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#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
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#define PACKET3_SET_CE_DE_COUNTERS 0x89
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#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
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#define PACKET3_SWITCH_BUFFER 0x8B
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#endif
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