drm/i915: Use plane state for primary plane updates.
Pass in the atomic states to allow for proper updates. This removes uses of intel_crtc->config and direct access to plane->state. This breaks the last bit of kgdboc, but that appears to be dead code. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1452164052-21752-7-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
parent
55a08b3f2b
commit
a8d201af68
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@ -652,9 +652,6 @@ struct drm_i915_display_funcs {
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struct drm_i915_gem_object *obj,
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struct drm_i915_gem_request *req,
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uint32_t flags);
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void (*update_primary_plane)(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y);
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void (*hpd_irq_setup)(struct drm_device *dev);
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/* clock updates for mode set */
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/* cursor updates */
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@ -2679,36 +2679,23 @@ valid_fb:
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obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
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}
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static void i9xx_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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static void i9xx_update_primary_plane(struct drm_plane *primary,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = primary->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_plane *primary = crtc->primary;
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bool visible = to_intel_plane_state(primary->state)->visible;
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struct drm_i915_gem_object *obj;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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int plane = intel_crtc->plane;
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unsigned long linear_offset;
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int x = plane_state->src.x1 >> 16;
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int y = plane_state->src.y1 >> 16;
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u32 dspcntr;
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i915_reg_t reg = DSPCNTR(plane);
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int pixel_size;
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if (!visible || !fb) {
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I915_WRITE(reg, 0);
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if (INTEL_INFO(dev)->gen >= 4)
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I915_WRITE(DSPSURF(plane), 0);
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else
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I915_WRITE(DSPADDR(plane), 0);
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POSTING_READ(reg);
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return;
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}
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obj = intel_fb_obj(fb);
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if (WARN_ON(obj == NULL))
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return;
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pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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@ -2723,13 +2710,13 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
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* which should always be the user's requested size.
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*/
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I915_WRITE(DSPSIZE(plane),
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((intel_crtc->config->pipe_src_h - 1) << 16) |
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(intel_crtc->config->pipe_src_w - 1));
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((crtc_state->pipe_src_h - 1) << 16) |
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(crtc_state->pipe_src_w - 1));
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I915_WRITE(DSPPOS(plane), 0);
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} else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
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I915_WRITE(PRIMSIZE(plane),
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((intel_crtc->config->pipe_src_h - 1) << 16) |
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(intel_crtc->config->pipe_src_w - 1));
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((crtc_state->pipe_src_h - 1) << 16) |
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(crtc_state->pipe_src_w - 1));
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I915_WRITE(PRIMPOS(plane), 0);
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I915_WRITE(PRIMCNSTALPHA(plane), 0);
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}
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@ -2780,17 +2767,17 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
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intel_crtc->dspaddr_offset = linear_offset;
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}
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if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
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if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
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dspcntr |= DISPPLANE_ROTATE_180;
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x += (intel_crtc->config->pipe_src_w - 1);
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y += (intel_crtc->config->pipe_src_h - 1);
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x += (crtc_state->pipe_src_w - 1);
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y += (crtc_state->pipe_src_h - 1);
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/* Finding the last pixel of the last line of the display
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data and adding to linear_offset*/
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linear_offset +=
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(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
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(intel_crtc->config->pipe_src_w - 1) * pixel_size;
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(crtc_state->pipe_src_h - 1) * fb->pitches[0] +
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(crtc_state->pipe_src_w - 1) * pixel_size;
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}
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intel_crtc->adjusted_x = x;
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@ -2809,37 +2796,40 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
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POSTING_READ(reg);
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}
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static void ironlake_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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static void i9xx_disable_primary_plane(struct drm_plane *primary,
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struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_plane *primary = crtc->primary;
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bool visible = to_intel_plane_state(primary->state)->visible;
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struct drm_i915_gem_object *obj;
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int plane = intel_crtc->plane;
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I915_WRITE(DSPCNTR(plane), 0);
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if (INTEL_INFO(dev_priv)->gen >= 4)
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I915_WRITE(DSPSURF(plane), 0);
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else
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I915_WRITE(DSPADDR(plane), 0);
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POSTING_READ(DSPCNTR(plane));
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}
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static void ironlake_update_primary_plane(struct drm_plane *primary,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = primary->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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int plane = intel_crtc->plane;
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unsigned long linear_offset;
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u32 dspcntr;
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i915_reg_t reg = DSPCNTR(plane);
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int pixel_size;
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if (!visible || !fb) {
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I915_WRITE(reg, 0);
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I915_WRITE(DSPSURF(plane), 0);
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POSTING_READ(reg);
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return;
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}
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obj = intel_fb_obj(fb);
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if (WARN_ON(obj == NULL))
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return;
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pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
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int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
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int x = plane_state->src.x1 >> 16;
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int y = plane_state->src.y1 >> 16;
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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dspcntr |= DISPLAY_PLANE_ENABLE;
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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@ -2881,18 +2871,18 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
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pixel_size,
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fb->pitches[0]);
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linear_offset -= intel_crtc->dspaddr_offset;
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if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
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if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
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dspcntr |= DISPPLANE_ROTATE_180;
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if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
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x += (intel_crtc->config->pipe_src_w - 1);
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y += (intel_crtc->config->pipe_src_h - 1);
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x += (crtc_state->pipe_src_w - 1);
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y += (crtc_state->pipe_src_h - 1);
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/* Finding the last pixel of the last line of the display
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data and adding to linear_offset*/
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linear_offset +=
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(intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
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(intel_crtc->config->pipe_src_w - 1) * pixel_size;
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(crtc_state->pipe_src_h - 1) * fb->pitches[0] +
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(crtc_state->pipe_src_w - 1) * pixel_size;
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}
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}
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@ -3083,36 +3073,30 @@ u32 skl_plane_ctl_rotation(unsigned int rotation)
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return 0;
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}
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static void skylake_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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static void skylake_update_primary_plane(struct drm_plane *plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_plane *plane = crtc->primary;
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bool visible = to_intel_plane_state(plane->state)->visible;
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struct drm_i915_gem_object *obj;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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int pipe = intel_crtc->pipe;
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u32 plane_ctl, stride_div, stride;
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u32 tile_height, plane_offset, plane_size;
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unsigned int rotation;
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unsigned int rotation = plane_state->base.rotation;
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int x_offset, y_offset;
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u32 surf_addr;
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struct intel_crtc_state *crtc_state = intel_crtc->config;
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struct intel_plane_state *plane_state;
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int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
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int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
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int scaler_id = -1;
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plane_state = to_intel_plane_state(plane->state);
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if (!visible || !fb) {
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I915_WRITE(PLANE_CTL(pipe, 0), 0);
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I915_WRITE(PLANE_SURF(pipe, 0), 0);
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POSTING_READ(PLANE_CTL(pipe, 0));
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return;
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}
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int scaler_id = plane_state->scaler_id;
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int src_x = plane_state->src.x1 >> 16;
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int src_y = plane_state->src.y1 >> 16;
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int src_w = drm_rect_width(&plane_state->src) >> 16;
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int src_h = drm_rect_height(&plane_state->src) >> 16;
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int dst_x = plane_state->dst.x1;
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int dst_y = plane_state->dst.y1;
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int dst_w = drm_rect_width(&plane_state->dst);
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int dst_h = drm_rect_height(&plane_state->dst);
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plane_ctl = PLANE_CTL_ENABLE |
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PLANE_CTL_PIPE_GAMMA_ENABLE |
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plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
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plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
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plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
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rotation = plane->state->rotation;
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plane_ctl |= skl_plane_ctl_rotation(rotation);
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obj = intel_fb_obj(fb);
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stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
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fb->pixel_format);
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surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
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WARN_ON(drm_rect_width(&plane_state->src) == 0);
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scaler_id = plane_state->scaler_id;
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src_x = plane_state->src.x1 >> 16;
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src_y = plane_state->src.y1 >> 16;
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src_w = drm_rect_width(&plane_state->src) >> 16;
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src_h = drm_rect_height(&plane_state->src) >> 16;
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dst_x = plane_state->dst.x1;
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dst_y = plane_state->dst.y1;
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dst_w = drm_rect_width(&plane_state->dst);
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dst_h = drm_rect_height(&plane_state->dst);
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WARN_ON(x != src_x || y != src_y);
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if (intel_rotation_90_or_270(rotation)) {
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/* stride = Surface height in tiles */
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tile_height = intel_tile_height(dev, fb->pixel_format,
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fb->modifier[0], 0);
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stride = DIV_ROUND_UP(fb->height, tile_height);
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x_offset = stride * tile_height - y - src_h;
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y_offset = x;
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x_offset = stride * tile_height - src_y - src_h;
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y_offset = src_x;
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plane_size = (src_w - 1) << 16 | (src_h - 1);
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} else {
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stride = fb->pitches[0] / stride_div;
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x_offset = x;
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y_offset = y;
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x_offset = src_x;
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y_offset = src_y;
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plane_size = (src_h - 1) << 16 | (src_w - 1);
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}
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plane_offset = y_offset << 16 | x_offset;
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@ -3188,20 +3157,30 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
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POSTING_READ(PLANE_SURF(pipe, 0));
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}
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static void skylake_disable_primary_plane(struct drm_plane *primary,
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struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = to_intel_crtc(crtc)->pipe;
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if (dev_priv->fbc.deactivate)
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dev_priv->fbc.deactivate(dev_priv);
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I915_WRITE(PLANE_CTL(pipe, 0), 0);
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I915_WRITE(PLANE_SURF(pipe, 0), 0);
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POSTING_READ(PLANE_SURF(pipe, 0));
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}
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/* Assume fb object is pinned & idle & fenced and just update base pointers */
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static int
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intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int x, int y, enum mode_set_atomic state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* Support for kgdboc is disabled, this needs a major rework. */
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DRM_ERROR("legacy panic handler not supported any more.\n");
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if (dev_priv->fbc.deactivate)
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dev_priv->fbc.deactivate(dev_priv);
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dev_priv->display.update_primary_plane(crtc, fb, x, y);
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return 0;
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return -ENODEV;
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}
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static void intel_complete_page_flips(struct drm_device *dev)
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@ -3228,8 +3207,10 @@ static void intel_update_primary_planes(struct drm_device *dev)
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drm_modeset_lock_crtc(crtc, &plane->base);
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plane_state = to_intel_plane_state(plane->base.state);
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if (crtc->state->active && plane_state->base.fb)
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plane->commit_plane(&plane->base, plane_state);
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if (plane_state->visible)
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plane->update_plane(&plane->base,
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to_intel_crtc_state(crtc->state),
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plane_state);
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drm_modeset_unlock_crtc(crtc);
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}
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@ -14037,32 +14018,6 @@ intel_check_primary_plane(struct drm_plane *plane,
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&state->visible);
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}
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static void
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intel_commit_primary_plane(struct drm_plane *plane,
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struct intel_plane_state *state)
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{
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struct drm_crtc *crtc = state->base.crtc;
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struct drm_framebuffer *fb = state->base.fb;
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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crtc = crtc ? crtc : plane->crtc;
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dev_priv->display.update_primary_plane(crtc, fb,
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state->src.x1 >> 16,
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state->src.y1 >> 16);
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}
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static void
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intel_disable_primary_plane(struct drm_plane *plane,
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struct drm_crtc *crtc)
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{
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
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}
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static void intel_begin_crtc_commit(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
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{
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@ -14147,20 +14102,33 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
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primary->plane = pipe;
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primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
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primary->check_plane = intel_check_primary_plane;
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primary->commit_plane = intel_commit_primary_plane;
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primary->disable_plane = intel_disable_primary_plane;
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
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primary->plane = !pipe;
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if (INTEL_INFO(dev)->gen >= 9) {
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intel_primary_formats = skl_primary_formats;
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num_formats = ARRAY_SIZE(skl_primary_formats);
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primary->update_plane = skylake_update_primary_plane;
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primary->disable_plane = skylake_disable_primary_plane;
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} else if (HAS_PCH_SPLIT(dev)) {
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intel_primary_formats = i965_primary_formats;
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num_formats = ARRAY_SIZE(i965_primary_formats);
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primary->update_plane = ironlake_update_primary_plane;
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primary->disable_plane = i9xx_disable_primary_plane;
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} else if (INTEL_INFO(dev)->gen >= 4) {
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intel_primary_formats = i965_primary_formats;
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num_formats = ARRAY_SIZE(i965_primary_formats);
|
||||
|
||||
primary->update_plane = i9xx_update_primary_plane;
|
||||
primary->disable_plane = i9xx_disable_primary_plane;
|
||||
} else {
|
||||
intel_primary_formats = i8xx_primary_formats;
|
||||
num_formats = ARRAY_SIZE(i8xx_primary_formats);
|
||||
|
||||
primary->update_plane = i9xx_update_primary_plane;
|
||||
primary->disable_plane = i9xx_disable_primary_plane;
|
||||
}
|
||||
|
||||
drm_universal_plane_init(dev, &primary->base, 0,
|
||||
|
@ -14988,8 +14956,6 @@ static void intel_init_display(struct drm_device *dev)
|
|||
haswell_crtc_compute_clock;
|
||||
dev_priv->display.crtc_enable = haswell_crtc_enable;
|
||||
dev_priv->display.crtc_disable = haswell_crtc_disable;
|
||||
dev_priv->display.update_primary_plane =
|
||||
skylake_update_primary_plane;
|
||||
} else if (HAS_DDI(dev)) {
|
||||
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
|
||||
dev_priv->display.get_initial_plane_config =
|
||||
|
@ -14998,8 +14964,6 @@ static void intel_init_display(struct drm_device *dev)
|
|||
haswell_crtc_compute_clock;
|
||||
dev_priv->display.crtc_enable = haswell_crtc_enable;
|
||||
dev_priv->display.crtc_disable = haswell_crtc_disable;
|
||||
dev_priv->display.update_primary_plane =
|
||||
ironlake_update_primary_plane;
|
||||
} else if (HAS_PCH_SPLIT(dev)) {
|
||||
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
|
||||
dev_priv->display.get_initial_plane_config =
|
||||
|
@ -15008,8 +14972,6 @@ static void intel_init_display(struct drm_device *dev)
|
|||
ironlake_crtc_compute_clock;
|
||||
dev_priv->display.crtc_enable = ironlake_crtc_enable;
|
||||
dev_priv->display.crtc_disable = ironlake_crtc_disable;
|
||||
dev_priv->display.update_primary_plane =
|
||||
ironlake_update_primary_plane;
|
||||
} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
|
||||
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
|
||||
dev_priv->display.get_initial_plane_config =
|
||||
|
@ -15017,8 +14979,6 @@ static void intel_init_display(struct drm_device *dev)
|
|||
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
|
||||
dev_priv->display.crtc_enable = valleyview_crtc_enable;
|
||||
dev_priv->display.crtc_disable = i9xx_crtc_disable;
|
||||
dev_priv->display.update_primary_plane =
|
||||
i9xx_update_primary_plane;
|
||||
} else {
|
||||
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
|
||||
dev_priv->display.get_initial_plane_config =
|
||||
|
@ -15026,8 +14986,6 @@ static void intel_init_display(struct drm_device *dev)
|
|||
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
|
||||
dev_priv->display.crtc_enable = i9xx_crtc_enable;
|
||||
dev_priv->display.crtc_disable = i9xx_crtc_disable;
|
||||
dev_priv->display.update_primary_plane =
|
||||
i9xx_update_primary_plane;
|
||||
}
|
||||
|
||||
/* Returns the core display clock speed */
|
||||
|
|
Loading…
Reference in a new issue