dt-bindings: display: fsl-imx-drm: Add i.MX8 DPR(Display Prefetch Resolve) support
The Display Prefetch Resolve(DPR) is a processor of fetching display data before the display pipeline which needs data to drive pixels in the active display region. The data is transformed, or resolved from a variety of tiled buffer formats into linear format. The DPR transaction sequences are issued with a high level of DRAM efficiency. This patch adds device tree binding doc support for i.MX8qm/qxp DPR. Signed-off-by: Liu Ying <victor.liu@nxp.com>5.4-rM2-2.2.x-imx-squashed
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@ -268,6 +268,37 @@ prg@56040000 {
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power-domains = <&pd IMX_SC_R_DC_0>;
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};
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Freescale i.MX8 DPRC (Display Prefetch Resolve Channel)
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=======================================================
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Required properties:
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- compatible: should be "fsl,<chip>-dpr-channel"
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- reg: should be register base and length as documented in the
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datasheet
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- fsl,sc-resource: SCU resource number as defined in
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include/dt-bindings/firmware/imx/rsrc.h
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- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one
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is the primary PRG and the second one(if available) is the auxiliary PRG
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which is used to fetch luma chunk of a YUV frame with 2 planars.
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- clocks: phandles to the DPRC apb, b and rtram clocks, as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
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- clock-names: should be "apb", "b" and "rtram"
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- power-domains: phandle pointing to power domain
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example:
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dpr-channel@560e0000 {
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compatible = "fsl,imx8qm-dpr-channel";
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reg = <0x560e0000 0x10000>;
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fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>;
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fsl,prgs = <&dc0_prg2>, <&dc0_prg1>;
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clocks = <&dc0_dpr0_lpcg 0>,
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<&dc0_dpr0_lpcg 1>,
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<&dc0_rtram0_lpcg 0>;
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clock-names = "apb", "b", "rtram";
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power-domains = <&pd IMX_SC_R_DC_0>;
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};
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Parallel display support
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========================
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