ath10k: add provision for Rx descriptor abstraction
There are slight differences in Rx hw descriptor information among different chips. So far driver does not use those new information for any functionalities, but there is one important information which is available from QCA99X0 onwards to indicate the number of bytes that hw padded at the begining of the rx payload and this information is needed to undecap the rx packet. Add an abstraction for Rx desc to make use of the new desc information available. The callback that this patch defines to retrieve the padding bytes will be used in follow-up patch. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [Rename operations to hw_ops for other purposes] Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -68,6 +68,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA988X_BOARD_DATA_SZ,
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.board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA9887_HW_1_0_VERSION,
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@ -87,6 +88,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA9887_BOARD_DATA_SZ,
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.board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA6174_HW_2_1_VERSION,
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@ -104,6 +106,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA6174_BOARD_DATA_SZ,
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.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA6174_HW_2_1_VERSION,
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@ -122,6 +125,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA6174_BOARD_DATA_SZ,
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.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA6174_HW_3_0_VERSION,
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@ -140,6 +144,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA6174_BOARD_DATA_SZ,
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.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA6174_HW_3_2_VERSION,
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@ -159,6 +164,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA6174_BOARD_DATA_SZ,
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.board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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@ -183,6 +189,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
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},
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.sw_decrypt_mcast_mgmt = true,
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.hw_ops = &qca99x0_ops,
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},
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{
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.id = QCA9984_HW_1_0_DEV_VERSION,
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@ -207,6 +214,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
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},
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.sw_decrypt_mcast_mgmt = true,
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.hw_ops = &qca99x0_ops,
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},
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{
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.id = QCA9888_HW_2_0_DEV_VERSION,
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@ -230,6 +238,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
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},
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.sw_decrypt_mcast_mgmt = true,
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.hw_ops = &qca99x0_ops,
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},
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{
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.id = QCA9377_HW_1_0_DEV_VERSION,
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@ -247,6 +256,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA9377_BOARD_DATA_SZ,
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.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA9377_HW_1_1_DEV_VERSION,
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@ -264,6 +274,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_size = QCA9377_BOARD_DATA_SZ,
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.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
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},
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.hw_ops = &qca988x_ops,
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},
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{
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.id = QCA4019_HW_1_0_DEV_VERSION,
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@ -289,6 +300,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
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},
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.sw_decrypt_mcast_mgmt = true,
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.hw_ops = &qca99x0_ops,
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},
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};
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@ -219,3 +219,16 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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survey->time = CCNT_TO_MSEC(ar, cc);
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survey->time_busy = CCNT_TO_MSEC(ar, rcc);
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}
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const struct ath10k_hw_ops qca988x_ops = {
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};
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static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
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{
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return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),
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RX_MSDU_END_INFO1_L3_HDR_PAD);
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}
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const struct ath10k_hw_ops qca99x0_ops = {
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.rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
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};
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@ -414,8 +414,20 @@ struct ath10k_hw_params {
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* frames encrypted and expect software do decryption.
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*/
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bool sw_decrypt_mcast_mgmt;
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const struct ath10k_hw_ops *hw_ops;
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};
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struct htt_rx_desc;
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/* Defines needed for Rx descriptor abstraction */
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struct ath10k_hw_ops {
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int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
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};
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extern const struct ath10k_hw_ops qca988x_ops;
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extern const struct ath10k_hw_ops qca99x0_ops;
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/* Target specific defines for MAIN firmware */
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#define TARGET_NUM_VDEVS 8
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#define TARGET_NUM_PEER_AST 2
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