sh: se7780 PCI support.
Add support for the SH7780 PCIC on the Solution Engine 7780, missing from the previous board-support patch. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Nobuhiro Iwamatsu
Paul Mundt
parent
b75762302e
commit
b7aee517c8
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@ -19,3 +19,4 @@ obj-$(CONFIG_SH_HIGHLANDER) += ops-r7780rp.o fixups-r7780rp.o
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obj-$(CONFIG_SH_TITAN) += ops-titan.o
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obj-$(CONFIG_SH_LANDISK) += ops-landisk.o
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obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o
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obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-se7780.o
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60
arch/sh/drivers/pci/fixups-se7780.c
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60
arch/sh/drivers/pci/fixups-se7780.c
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@ -0,0 +1,60 @@
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/*
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* arch/sh/drivers/pci/fixups-se7780.c
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*
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* HITACHI UL Solution Engine 7780 PCI fixups
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*
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* Copyright (C) 2003 Lineo uSolutions, Inc.
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* Copyright (C) 2004 - 2006 Paul Mundt
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* Copyright (C) 2006 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pci.h>
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#include "pci-sh4.h"
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#include <asm/io.h>
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int pci_fixup_pcic(void)
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{
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ctrl_outl(0x00000001, SH7780_PCI_VCR2);
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/* Enable all interrupts, so we know what to fix */
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pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
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pci_write_reg(0x0000380F, SH7780_PCIAINTM);
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/* Set up standard PCI config registers */
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ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
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ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
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ctrl_outb( 0x00, PCI_REG(SH7780_PCIPIF));
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ctrl_outb( 0x00, PCI_REG(SH7780_PCISUB));
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ctrl_outb( 0x06, PCI_REG(SH7780_PCIBCC));
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ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
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ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
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pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
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pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
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pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
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pci_write_reg(0x00000000, SH7780_PCIMBAR1);
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pci_write_reg(0x00000000, SH7780_PCILAR1);
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pci_write_reg(0x00000000, SH7780_PCILSR1);
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pci_write_reg(0xAB000801, SH7780_PCIIBAR);
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/*
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* Set the MBR so PCI address is one-to-one with window,
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* meaning all calls go straight through... use ifdef to
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* catch erroneous assumption.
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*/
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pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
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pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
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/* Set IOBR for window containing area specified in pci.h */
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pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
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pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
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pci_write_reg(0xA5000C01, SH7780_PCICR);
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return 0;
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}
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96
arch/sh/drivers/pci/ops-se7780.c
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96
arch/sh/drivers/pci/ops-se7780.c
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@ -0,0 +1,96 @@
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/*
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* linux/arch/sh/drivers/pci/ops-se7780.c
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*
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* Copyright (C) 2006 Nobuhiro Iwamatsu
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*
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* PCI initialization for the Hitachi UL Solution Engine 7780SE03
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <asm/se7780.h>
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#include <asm/io.h>
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#include "pci-sh4.h"
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/*
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* IDSEL = AD16 PCI slot
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* IDSEL = AD17 PCI slot
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* IDSEL = AD18 Serial ATA Controller (Silicon Image SiL3512A)
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* IDSEL = AD19 USB Host Controller (NEC uPD7210100A)
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*/
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/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
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static char se7780_irq_tab[4][16] __initdata = {
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/* INTA */
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{ 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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/* INTB */
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{ 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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/* INTC */
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{ 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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/* INTD */
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{ 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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};
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int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
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{
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return se7780_irq_tab[pin-1][slot];
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}
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static struct resource se7780_io_resource = {
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.name = "SH7780_IO",
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.start = 0x2000,
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.end = 0x2000 + SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource se7780_mem_resource = {
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.name = "SH7780_mem",
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.start = SH7780_PCI_MEMORY_BASE,
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.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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extern struct pci_ops se7780_pci_ops;
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struct pci_channel board_pci_channels[] = {
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{ &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },
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{ NULL, NULL, NULL, 0, 0 },
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};
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EXPORT_SYMBOL(board_pci_channels);
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static struct sh4_pci_address_map se7780_pci_map = {
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.window0 = {
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.base = SH7780_CS2_BASE_ADDR,
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.size = 0x04000000,
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},
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.flags = SH4_PCIC_NO_RESET,
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};
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int __init pcibios_init_platform(void)
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{
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printk("SH7780 PCI: Finished initialization of the PCI controller\n");
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/*
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* FPGA PCISEL register initialize
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*
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* CPU || SLOT1 | SLOT2 | S-ATA | USB
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* -------------------------------------
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* INTA || INTA | INTD | -- | INTB
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* -------------------------------------
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* INTB || INTB | INTA | -- | INTC
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* -------------------------------------
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* INTC || INTC | INTB | INTA | --
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* -------------------------------------
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* INTD || INTD | INTC | -- | INTA
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* -------------------------------------
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*/
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ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
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ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
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return sh7780_pcic_init(&se7780_pci_map);
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}
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