Qualcomm ARM Based Device Tree Updates for v3.16-2
* Updated MSM8660/MSM8960/MSM8974 dts for various updates or conformitity to binding specs * Added APQ8064 SoC and IFC6410 board device tree support * Added APQ8084 SoC and APQ8084-MTP board device tree support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: GPGTools - https://gpgtools.org iQIcBAABCgAGBQJTiLIDAAoJEF9hYXeAcXzBTZkQALpph9EDQz583BLIHabv5lCY mhRSCBS5j5CscM8o0euaqFcKIyNmFOuPCis2jArMmX9Z8RjRJod6zNzdQW92Kddq TXMtRo+BX1Jel9Ri5ysXGvDOkUeViUf56PuYy4pqFOEfbeKpH/yfWTAJDt2usIEi 9bfDodwAbbsB9t8IBgTNhyhAmMUqkfvBvtBnG8qAyXBxUkvC5iAjPnWT8LOisrTC hTIvh8H3acImN4TLlvElvhRDPC7a4rcmF7XdoCjm3F9t9b/7U2mwGCGqZGGal/p7 H7SvAwTfQcNToZeo9RMz+xxq0fT00qLQqnHtx7s0NXXA2XPVQ2RxNH2YUqBUGAEq EEfXjTh+pBUUfzLmxbBzuD9pNx5JD0rhIKV5sA/pCXabmEFQzXcIeGmKpSapbuOi 7zoqSqaqDlR21qdBuh545E6zIlSE7VPeeG0oqI2bzaG4OHksoRuMJhUzkKikHxQ8 uN+P5lPQudBT6FbncVvpGNuAkTVB6T7Qtl7jzCplLCgZ2T3X1gb0sg5+1R9vqOEz 1n9er/cAiaklv+ca4jsfCuQAkgrxAfqtPGPxyVo8fuaIE+Q97y38yWfCquxl1oGp vkE9s2TaREWbRCIvOf2Oxm0dFrTWWVjQI1kAq4iSJCDIBS7f1/qXtS0NvrE1E2+e B+9veuw7/7xIcSZZvb52 =u8HT -----END PGP SIGNATURE----- Merge tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt Merge "Qualcomm ARM Based Device Tree Updates for v3.16-2" from Kumar Gala: * Updated MSM8660/MSM8960/MSM8974 dts for various updates or conformitity to binding specs * Added APQ8064 SoC and IFC6410 board device tree support * Added APQ8084 SoC and APQ8084-MTP board device tree support * tag 'qcom-dt-for-3.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: ARM: dts: qcom: Add APQ8084-MTP board support ARM: dts: qcom: Add APQ8084 SoC support ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees ARM: dts: qcom: Update msm8660 device trees ARM: dts: qcom: Update msm8960 device trees ARM: dts: qcom: Update msm8974/apq8074 device trees Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Olof Johansson
commit
bb19501651
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@ -308,9 +308,12 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
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orion5x-maxtor-shared-storage-2.dtb \
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orion5x-rd88f5182-nas.dtb
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dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-apq8074-dragonboard.dtb
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dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8064-ifc6410.dtb \
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qcom-apq8074-dragonboard.dtb \
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qcom-apq8084-mtp.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb
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dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
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dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
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s3c6410-smdk6410.dtb
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@ -0,0 +1,16 @@
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#include "qcom-apq8064-v2.0.dtsi"
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/ {
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model = "Qualcomm APQ8064/IFC6410";
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compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
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soc {
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gsbi@16600000 {
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status = "ok";
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qcom,mode = <GSBI_PROT_I2C_UART>;
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serial@16640000 {
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status = "ok";
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};
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};
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};
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};
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@ -0,0 +1 @@
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#include "qcom-apq8064.dtsi"
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@ -0,0 +1,170 @@
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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model = "Qualcomm APQ8064";
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compatible = "qcom,apq8064";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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};
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cpu@2 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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};
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cpu@3 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 10 0x304>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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};
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timer@200a000 {
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x80000>;
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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acc2: clock-controller@20a8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
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};
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acc3: clock-controller@20b8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
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};
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saw0: regulator@2089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw1: regulator@2099000 {
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compatible = "qcom,saw2";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw2: regulator@20a9000 {
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compatible = "qcom,saw2";
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reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw3: regulator@20b9000 {
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compatible = "qcom,saw2";
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reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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gsbi7: gsbi@16600000 {
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status = "disabled";
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compatible = "qcom,gsbi-v1.0.0";
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reg = <0x16600000 0x100>;
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clocks = <&gcc GSBI7_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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serial@16640000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16640000 0x1000>,
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<0x16600000 0x1000>;
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interrupts = <0 158 0x0>;
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clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x00500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-apq8064";
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reg = <0x00900000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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};
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@ -4,7 +4,11 @@
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model = "Qualcomm APQ8074 Dragonboard";
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compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
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soc: soc {
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soc {
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serial@f991e000 {
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status = "ok";
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};
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sdhci@f9824900 {
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bus-width = <8>;
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non-removable;
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@ -15,5 +19,27 @@
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cd-gpios = <&msmgpio 62 0x1>;
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bus-width = <4>;
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};
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pinctrl@fd510000 {
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spi8_default: spi8_default {
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mosi {
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pins = "gpio45";
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function = "blsp_spi8";
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};
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miso {
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pins = "gpio46";
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function = "blsp_spi8";
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};
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cs {
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pins = "gpio47";
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function = "blsp_spi8";
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};
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clk {
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pins = "gpio48";
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function = "blsp_spi8";
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};
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};
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};
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};
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};
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@ -0,0 +1,6 @@
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#include "qcom-apq8084.dtsi"
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/ {
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model = "Qualcomm APQ 8084-MTP";
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compatible = "qcom,apq8084-mtp", "qcom,apq8084";
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};
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@ -0,0 +1,179 @@
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/dts-v1/;
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#include "skeleton.dtsi"
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/ {
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model = "Qualcomm APQ 8084";
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compatible = "qcom,apq8084";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <0>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <1>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <2>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "qcom,krait";
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reg = <3>;
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enable-method = "qcom,kpss-acc-v2";
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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};
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L2: l2-cache {
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compatible = "qcom,arch-cache";
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cache-level = <2>;
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qcom,saw = <&saw_l2>;
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};
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};
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 7 0xf04>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <19200000>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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};
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timer@f9020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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clock-frequency = <19200000>;
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <0 8 0x4>,
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<0 7 0x4>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <0 9 0x4>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <0 10 0x4>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <0 11 0x4>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <0 12 0x4>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <0 13 0x4>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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||||
};
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||||
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frame@f9028000 {
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frame-number = <6>;
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||||
interrupts = <0 14 0x4>;
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reg = <0xf9028000 0x1000>;
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||||
status = "disabled";
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||||
};
|
||||
};
|
||||
|
||||
saw_l2: regulator@f9012000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0xf9012000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
acc0: clock-controller@f9088000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0xf9088000 0x1000>,
|
||||
<0xf9008000 0x1000>;
|
||||
};
|
||||
|
||||
acc1: clock-controller@f9098000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0xf9098000 0x1000>,
|
||||
<0xf9008000 0x1000>;
|
||||
};
|
||||
|
||||
acc2: clock-controller@f90a8000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0xf90a8000 0x1000>,
|
||||
<0xf9008000 0x1000>;
|
||||
};
|
||||
|
||||
acc3: clock-controller@f90b8000 {
|
||||
compatible = "qcom,kpss-acc-v2";
|
||||
reg = <0xf90b8000 0x1000>,
|
||||
<0xf9008000 0x1000>;
|
||||
};
|
||||
|
||||
restart@fc4ab000 {
|
||||
compatible = "qcom,pshold";
|
||||
reg = <0xfc4ab000 0x4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -3,4 +3,14 @@
|
|||
/ {
|
||||
model = "Qualcomm MSM8660 SURF";
|
||||
compatible = "qcom,msm8660-surf", "qcom,msm8660";
|
||||
|
||||
soc {
|
||||
gsbi@19c00000 {
|
||||
status = "ok";
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
serial@19c40000 {
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
/include/ "skeleton.dtsi"
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM8660";
|
||||
|
|
@ -12,16 +13,18 @@
|
|||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "qcom,scorpion";
|
||||
enable-method = "qcom,gcc-msm8660";
|
||||
|
||||
cpu@0 {
|
||||
compatible = "qcom,scorpion";
|
||||
enable-method = "qcom,gcc-msm8660";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "qcom,scorpion";
|
||||
enable-method = "qcom,gcc-msm8660";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -33,55 +36,73 @@
|
|||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@2080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02080000 0x1000 >,
|
||||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
timer@2000000 {
|
||||
compatible = "qcom,scss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 0 0x301>,
|
||||
<1 1 0x301>,
|
||||
<1 2 0x301>;
|
||||
reg = <0x02000000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
intc: interrupt-controller@2080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02080000 0x1000 >,
|
||||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
|
||||
msmgpio: gpio@800000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
reg = <0x00800000 0x4000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpio = <173>;
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
timer@2000000 {
|
||||
compatible = "qcom,scss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 0 0x301>,
|
||||
<1 1 0x301>,
|
||||
<1 2 0x301>;
|
||||
reg = <0x02000000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8660";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x900000 0x4000>;
|
||||
};
|
||||
msmgpio: gpio@800000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
reg = <0x00800000 0x4000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpio = <173>;
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
serial@19c40000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
<0x19c00000 0x1000>;
|
||||
interrupts = <0 195 0x0>;
|
||||
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
};
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8660";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x900000 0x4000>;
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
gsbi12: gsbi@19c00000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
reg = <0x19c00000 0x100>;
|
||||
clocks = <&gcc GSBI12_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
serial@19c40000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
<0x19c00000 0x1000>;
|
||||
interrupts = <0 195 0x0>;
|
||||
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,4 +3,14 @@
|
|||
/ {
|
||||
model = "Qualcomm MSM8960 CDP";
|
||||
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
|
||||
|
||||
soc {
|
||||
gsbi@16400000 {
|
||||
status = "ok";
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
serial@16440000 {
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
/include/ "skeleton.dtsi"
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM8960";
|
||||
|
|
@ -13,10 +14,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <1 14 0x304>;
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v1";
|
||||
|
||||
cpu@0 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v1";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -25,6 +26,8 @@
|
|||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v1";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -35,7 +38,6 @@
|
|||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
interrupts = <0 2 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -45,91 +47,109 @@
|
|||
qcom,no-pc-write;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02000000 0x1000 >,
|
||||
< 0x02002000 0x1000 >;
|
||||
};
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
timer@200a000 {
|
||||
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>,
|
||||
<1 2 0x301>,
|
||||
<1 3 0x301>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
intc: interrupt-controller@2000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x02000000 0x1000>,
|
||||
<0x02002000 0x1000>;
|
||||
};
|
||||
|
||||
msmgpio: gpio@800000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpio = <150>;
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800000 0x4000>;
|
||||
};
|
||||
timer@200a000 {
|
||||
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>,
|
||||
<1 2 0x301>,
|
||||
<1 3 0x301>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x900000 0x4000>;
|
||||
};
|
||||
msmgpio: gpio@800000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpio = <150>;
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800000 0x4000>;
|
||||
};
|
||||
|
||||
clock-controller@4000000 {
|
||||
compatible = "qcom,mmcc-msm8960";
|
||||
reg = <0x4000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x900000 0x4000>;
|
||||
};
|
||||
|
||||
acc0: clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
};
|
||||
clock-controller@4000000 {
|
||||
compatible = "qcom,mmcc-msm8960";
|
||||
reg = <0x4000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
acc1: clock-controller@2098000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
||||
};
|
||||
acc0: clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
};
|
||||
|
||||
saw0: regulator@2089000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
acc1: clock-controller@2098000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
||||
};
|
||||
|
||||
saw1: regulator@2099000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
saw0: regulator@2089000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
serial@16440000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16440000 0x1000>,
|
||||
<0x16400000 0x1000>;
|
||||
interrupts = <0 154 0x0>;
|
||||
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
};
|
||||
saw1: regulator@2099000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
};
|
||||
gsbi5: gsbi@16400000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
reg = <0x16400000 0x100>;
|
||||
clocks = <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
rng@1a500000 {
|
||||
compatible = "qcom,prng";
|
||||
reg = <0x1a500000 0x200>;
|
||||
clocks = <&gcc PRNG_CLK>;
|
||||
clock-names = "core";
|
||||
serial@16440000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16440000 0x1000>,
|
||||
<0x16400000 0x1000>;
|
||||
interrupts = <0 154 0x0>;
|
||||
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
};
|
||||
|
||||
rng@1a500000 {
|
||||
compatible = "qcom,prng";
|
||||
reg = <0x1a500000 0x200>;
|
||||
clocks = <&gcc PRNG_CLK>;
|
||||
clock-names = "core";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,10 +13,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v2";
|
||||
|
||||
cpu@0 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v2";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -24,6 +24,8 @@
|
|||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v2";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -31,6 +33,8 @@
|
|||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v2";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -38,6 +42,8 @@
|
|||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v2";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -47,7 +53,6 @@
|
|||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
interrupts = <0 2 0x4>;
|
||||
qcom,saw = <&saw_l2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -57,6 +62,15 @@
|
|||
interrupts = <1 7 0xf04>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 2 0xf08>,
|
||||
<1 3 0xf08>,
|
||||
<1 4 0xf08>,
|
||||
<1 1 0xf08>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -71,15 +85,6 @@
|
|||
<0xf9002000 0x1000>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 2 0xf08>,
|
||||
<1 3 0xf08>,
|
||||
<1 4 0xf08>,
|
||||
<1 1 0xf08>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
timer@f9020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -190,6 +195,7 @@
|
|||
interrupts = <0 108 0x0>;
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@f9824900 {
|
||||
|
|
@ -229,25 +235,6 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 208 0>;
|
||||
|
||||
spi8_default: spi8_default {
|
||||
mosi {
|
||||
pins = "gpio45";
|
||||
function = "blsp_spi8";
|
||||
};
|
||||
miso {
|
||||
pins = "gpio46";
|
||||
function = "blsp_spi8";
|
||||
};
|
||||
cs {
|
||||
pins = "gpio47";
|
||||
function = "blsp_spi8";
|
||||
};
|
||||
clk {
|
||||
pins = "gpio48";
|
||||
function = "blsp_spi8";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,9 +15,11 @@
|
|||
#include <asm/mach/arch.h>
|
||||
|
||||
static const char * const qcom_dt_match[] __initconst = {
|
||||
"qcom,apq8064",
|
||||
"qcom,apq8074-dragonboard",
|
||||
"qcom,apq8084",
|
||||
"qcom,msm8660-surf",
|
||||
"qcom,msm8960-cdp",
|
||||
"qcom,apq8074-dragonboard",
|
||||
NULL
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue