ARM: mvebu: Simplify headers and make local
kirkwood is very nearly fully DT. Remove most of the address definitions from the header files and make it a local header file. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>hifive-unleashed-5.1
Andrew Lunn
Jason Cooper
parent
97171ad70e
commit
c3f08d0d59
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@ -1,85 +0,0 @@
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/*
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* arch/arm/mach-mvebu/include/mach/bridge-regs.h
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*
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* Mbus-L to Mbus Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/kirkwood.h>
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#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
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#define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
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#define CPU_CONFIG_ERROR_PROP 0x00000004
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#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
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#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
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#define CPU_RESET 0x00000002
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
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#define CGC_BIT_GE0 (0)
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#define CGC_BIT_PEX0 (2)
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#define CGC_BIT_USB0 (3)
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#define CGC_BIT_SDIO (4)
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#define CGC_BIT_TSU (5)
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#define CGC_BIT_DUNIT (6)
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#define CGC_BIT_RUNIT (7)
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#define CGC_BIT_XOR0 (8)
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#define CGC_BIT_AUDIO (9)
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#define CGC_BIT_SATA0 (14)
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#define CGC_BIT_SATA1 (15)
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#define CGC_BIT_XOR1 (16)
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#define CGC_BIT_CRYPTO (17)
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#define CGC_BIT_PEX1 (18)
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#define CGC_BIT_GE1 (19)
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#define CGC_BIT_TDM (20)
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#define CGC_GE0 (1 << 0)
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#define CGC_PEX0 (1 << 2)
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#define CGC_USB0 (1 << 3)
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#define CGC_SDIO (1 << 4)
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#define CGC_TSU (1 << 5)
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#define CGC_DUNIT (1 << 6)
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#define CGC_RUNIT (1 << 7)
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#define CGC_XOR0 (1 << 8)
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#define CGC_AUDIO (1 << 9)
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#define CGC_POWERSAVE (1 << 11)
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#define CGC_SATA0 (1 << 14)
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#define CGC_SATA1 (1 << 15)
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#define CGC_XOR1 (1 << 16)
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#define CGC_CRYPTO (1 << 17)
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#define CGC_PEX1 (1 << 18)
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#define CGC_GE1 (1 << 19)
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#define CGC_TDM (1 << 20)
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#define CGC_RESERVED (0x6 << 21)
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#define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118)
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#define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x118)
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#endif
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@ -1,142 +0,0 @@
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/*
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* arch/arm/mach-mvebu/include/mach/kirkwood.h
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*
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* Generic definitions for Marvell Kirkwood SoC flavors:
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* 88F6180, 88F6192 and 88F6281.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_KIRKWOOD_H
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#define __ASM_ARCH_KIRKWOOD_H
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/*
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* Marvell Kirkwood address maps.
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*
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* phys
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* e0000000 PCIe #0 Memory space
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* e8000000 PCIe #1 Memory space
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* f1000000 on-chip peripheral registers
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* f2000000 PCIe #0 I/O space
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* f3000000 PCIe #1 I/O space
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* f4000000 NAND controller address window
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* f5000000 Security Accelerator SRAM
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*
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* virt phys size
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* fed00000 f1000000 1M on-chip peripheral registers
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* fee00000 f2000000 1M PCIe #0 I/O space
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* fef00000 f3000000 1M PCIe #1 I/O space
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*/
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#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
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#define KIRKWOOD_SRAM_SIZE SZ_2K
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#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
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#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
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#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
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#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000
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#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K
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#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
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#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
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#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
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#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
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#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000)
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#define KIRKWOOD_REGS_SIZE SZ_1M
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#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
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#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
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#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
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#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
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/*
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* Register Map
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*/
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#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
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#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
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#define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500)
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#define DDR_WINDOW_CPU_SZ (0x20)
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#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
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#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
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#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
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#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030)
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#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034)
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#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
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#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140)
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#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300)
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#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600)
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#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
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#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
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#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
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#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
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#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
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#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
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#define BRIDGE_WINS_SZ (0x80)
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#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
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#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
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#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70)
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#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04)
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#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
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#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70)
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#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04)
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#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
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#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
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#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
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#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
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#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
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#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
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#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
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#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
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#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
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#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
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#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
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#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
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#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
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#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050)
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#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330)
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#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050)
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#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330)
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#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
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#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
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#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
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/*
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* Supported devices and revisions.
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*/
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#define MV88F6281_DEV_ID 0x6281
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#define MV88F6281_REV_Z0 0
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#define MV88F6281_REV_A0 2
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#define MV88F6281_REV_A1 3
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#define MV88F6192_DEV_ID 0x6192
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#define MV88F6192_REV_Z0 0
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#define MV88F6192_REV_A0 2
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#define MV88F6192_REV_A1 3
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#define MV88F6180_DEV_ID 0x6180
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#define MV88F6180_REV_A0 2
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#define MV88F6180_REV_A1 3
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#define MV88F6282_DEV_ID 0x6282
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#define MV88F6282_REV_A0 0
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#define MV88F6282_REV_A1 1
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#endif
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@ -17,7 +17,7 @@
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#include <linux/kernel.h>
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#include <linux/suspend.h>
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#include <linux/io.h>
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#include <mach/bridge-regs.h>
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#include "kirkwood.h"
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static void __iomem *ddr_operation_base;
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static void __iomem *memory_pm_ctrl;
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@ -13,19 +13,16 @@
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_net.h>
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#include <linux/of_platform.h>
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#include <linux/dma-mapping.h>
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#include <linux/irqchip.h>
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#include <linux/kexec.h>
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#include <linux/slab.h>
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#include <asm/hardware/cache-feroceon-l2.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/bridge-regs.h>
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#include <plat/common.h>
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#include <plat/pcie.h>
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#include "kirkwood.h"
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#include "kirkwood-pm.h"
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#include "common.h"
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@ -0,0 +1,22 @@
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/*
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* arch/arm/mach-mvebu/kirkwood.h
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*
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* Generic definitions for Marvell Kirkwood SoC flavors:
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* 88F6180, 88F6192 and 88F6281.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
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#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
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#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
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#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
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#define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
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#define CPU_CONFIG_ERROR_PROP 0x00000004
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#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
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#define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118)
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