drm/radeon: add rptr save support for r1xx-r5xx
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -1060,6 +1060,14 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
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}
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ring->ready = true;
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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if (radeon_ring_supports_scratch_reg(rdev, ring)) {
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r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
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if (r) {
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DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
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ring->rptr_save_reg = 0;
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}
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}
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return 0;
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}
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@ -1070,6 +1078,7 @@ void r100_cp_fini(struct radeon_device *rdev)
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}
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/* Disable ring */
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r100_cp_disable(rdev);
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radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
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radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
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DRM_INFO("radeon: cp finalized\n");
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}
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@ -3661,6 +3670,12 @@ void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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if (ring->rptr_save_reg) {
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u32 next_rptr = ring->wptr + 2 + 3;
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radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
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radeon_ring_write(ring, next_rptr);
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}
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radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
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radeon_ring_write(ring, ib->gpu_addr);
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radeon_ring_write(ring, ib->length_dw);
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