drm/i915: Remove checks for cloned config with LVDS in dpll code
LVDS is not cloneable, so the check is unnecessary. Removing it makes the code neater. v2: Remove checks from GMCH code too, not only ILK+. (Ville) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-2-git-send-email-ander.conselvan.de.oliveira@intel.com
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@ -111,8 +111,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
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static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
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static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state);
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static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
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int num_connectors);
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static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state);
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static void skylake_pfit_enable(struct intel_crtc *crtc);
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static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
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static void ironlake_pfit_enable(struct intel_crtc *crtc);
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@ -1074,7 +1073,7 @@ chv_find_best_dpll(const intel_limit_t *limit,
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bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
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intel_clock_t *best_clock)
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{
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int refclk = i9xx_get_refclk(crtc_state, 0);
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int refclk = i9xx_get_refclk(crtc_state);
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return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
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target_clock, refclk, NULL, best_clock);
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@ -7058,8 +7057,7 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
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&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
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}
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static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
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int num_connectors)
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static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -7070,7 +7068,7 @@ static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
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if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
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refclk = 100000;
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} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
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intel_panel_use_ssc(dev_priv)) {
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refclk = dev_priv->vbt.lvds_ssc_freq;
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
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} else if (!IS_GEN2(dev)) {
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@ -7511,8 +7509,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
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static void i9xx_compute_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *reduced_clock,
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int num_connectors)
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intel_clock_t *reduced_clock)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -7571,7 +7568,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
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if (crtc_state->sdvo_tv_clock)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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intel_panel_use_ssc(dev_priv))
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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@ -7588,8 +7585,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
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static void i8xx_compute_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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intel_clock_t *reduced_clock,
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int num_connectors)
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intel_clock_t *reduced_clock)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -7615,7 +7611,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
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dpll |= DPLL_DVO_2X_MODE;
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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intel_panel_use_ssc(dev_priv))
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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@ -7843,14 +7839,10 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int refclk, num_connectors = 0;
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int refclk;
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intel_clock_t clock;
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bool ok;
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const intel_limit_t *limit;
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struct drm_atomic_state *state = crtc_state->base.state;
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struct drm_connector *connector;
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struct drm_connector_state *connector_state;
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int i;
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memset(&crtc_state->dpll_hw_state, 0,
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sizeof(crtc_state->dpll_hw_state));
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@ -7858,13 +7850,8 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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if (crtc_state->has_dsi_encoder)
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return 0;
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for_each_connector_in_state(state, connector, connector_state, i) {
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if (connector_state->crtc == &crtc->base)
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num_connectors++;
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}
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if (!crtc_state->clock_set) {
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refclk = i9xx_get_refclk(crtc_state, num_connectors);
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refclk = i9xx_get_refclk(crtc_state);
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/*
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* Returns a set of divisors for the desired target clock with
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@ -7890,15 +7877,13 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
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}
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if (IS_GEN2(dev)) {
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i8xx_compute_dpll(crtc, crtc_state, NULL,
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num_connectors);
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i8xx_compute_dpll(crtc, crtc_state, NULL);
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} else if (IS_CHERRYVIEW(dev)) {
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chv_compute_dpll(crtc, crtc_state);
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} else if (IS_VALLEYVIEW(dev)) {
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vlv_compute_dpll(crtc, crtc_state);
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} else {
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i9xx_compute_dpll(crtc, crtc_state, NULL,
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num_connectors);
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i9xx_compute_dpll(crtc, crtc_state, NULL);
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}
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return 0;
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@ -8584,30 +8569,9 @@ static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_atomic_state *state = crtc_state->base.state;
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struct drm_connector *connector;
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struct drm_connector_state *connector_state;
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struct intel_encoder *encoder;
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int num_connectors = 0, i;
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bool is_lvds = false;
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for_each_connector_in_state(state, connector, connector_state, i) {
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if (connector_state->crtc != crtc_state->base.crtc)
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continue;
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encoder = to_intel_encoder(connector_state->best_encoder);
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switch (encoder->type) {
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case INTEL_OUTPUT_LVDS:
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is_lvds = true;
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break;
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default:
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break;
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}
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num_connectors++;
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}
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if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
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if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv)) {
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DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
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dev_priv->vbt.lvds_ssc_freq);
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return dev_priv->vbt.lvds_ssc_freq;
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@ -8768,7 +8732,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct drm_connector_state *connector_state;
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struct intel_encoder *encoder;
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uint32_t dpll;
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int factor, num_connectors = 0, i;
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int factor, i;
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bool is_lvds = false, is_sdvo = false;
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for_each_connector_in_state(state, connector, connector_state, i) {
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@ -8788,8 +8752,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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default:
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break;
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}
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num_connectors++;
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}
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/* Enable autotuning of the PLL clock (if permissible) */
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@ -8843,7 +8805,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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break;
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}
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if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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if (is_lvds && intel_panel_use_ssc(dev_priv))
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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