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clk: imx: scu: rename imx_clk_scu3 to imx_clk_gate_gpr_scu 

Like other scu gpr clocks, change the name to be more accurate.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Dong Aisheng 2019-07-19 16:07:24 +08:00
parent b93157db7f
commit cf94f27a37
3 changed files with 21 additions and 21 deletions
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4
drivers/clk/imx/clk-imx8qxp.c
View File

@ -142,13 +142,13 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_CONN_ENET0_RGMII_TXC_SEL] = imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
clks[IMX_CONN_ENET0_RGMII_RX_CLK] = imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
clks[IMX_CONN_ENET0_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet0_ref_50_clk", NULL, IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_ENET0_RMII_REF_50MHZ_CLK] = imx_clk_gate_gpr_scu("enet0_ref_50_clk", NULL, IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
clks[IMX_CONN_ENET1_REF_DIV] = imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
clks[IMX_CONN_ENET1_RGMII_TXC_SEL] = imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
clks[IMX_CONN_ENET1_RGMII_RX_CLK] = imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
clks[IMX_CONN_ENET1_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet1_ref_50_clk", NULL, IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_ENET1_RMII_REF_50MHZ_CLK] = imx_clk_gate_gpr_scu("enet1_ref_50_clk", NULL, IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);

36
drivers/clk/imx/clk-scu.c
View File

@ -77,12 +77,12 @@ struct clk_mux_gpr_scu {
};
/*
* struct clk_gate3_scu - Description of one gate SCU clock
* struct clk_gate_gpr_scu - Description of one gate SCU clock
* @hw: the common clk_hw
* @rsrc_id: resource ID of this SCU clock
* @gpr_id: GPR ID index to control the divider
*/
struct clk_gate3_scu {
struct clk_gate_gpr_scu {
struct clk_hw hw;
u16 rsrc_id;
u8 gpr_id;
@ -115,7 +115,7 @@ struct resp_get_clock_rate {
};
#define to_clk_mux_gpr_scu(_hw) container_of(_hw, struct clk_mux_gpr_scu, hw)
#define to_clk_gate3_scu(_hw) container_of(_hw, struct clk_gate3_scu, hw)
#define to_clk_gate_gpr_scu(_hw) container_of(_hw, struct clk_gate_gpr_scu, hw)
/*
* struct imx_sc_msg_get_clock_rate - clock get rate protocol
@ -379,9 +379,9 @@ struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char **parents,
return hw;
}
static int clk_gate3_scu_prepare(struct clk_hw *hw)
static int clk_gate_scu_gpr_prepare(struct clk_hw *hw)
{
struct clk_gate3_scu *gate = to_clk_gate3_scu(hw);
struct clk_gate_gpr_scu *gate = to_clk_gate_gpr_scu(hw);
uint32_t val;
if (!ccm_ipc_handle)
@ -394,9 +394,9 @@ static int clk_gate3_scu_prepare(struct clk_hw *hw)
}
/* Write to the LPCG bits. */
static void clk_gate3_scu_unprepare(struct clk_hw *hw)
static void clk_gate_scu_gpr_unprepare(struct clk_hw *hw)
{
struct clk_gate3_scu *gate = to_clk_gate3_scu(hw);
struct clk_gate_gpr_scu *gate = to_clk_gate_gpr_scu(hw);
uint32_t val;
if (!ccm_ipc_handle)
@ -407,9 +407,9 @@ static void clk_gate3_scu_unprepare(struct clk_hw *hw)
gate->gpr_id, val);
}
static int clk_gate3_scu_is_prepared(struct clk_hw *hw)
static int clk_gate_scu_gpr_is_prepared(struct clk_hw *hw)
{
struct clk_gate3_scu *gate = to_clk_gate3_scu(hw);
struct clk_gate_gpr_scu *gate = to_clk_gate_gpr_scu(hw);
uint32_t val;
if (!ccm_ipc_handle)
@ -425,16 +425,16 @@ static int clk_gate3_scu_is_prepared(struct clk_hw *hw)
return val;
}
static struct clk_ops clk_gate3_scu_ops = {
.prepare = clk_gate3_scu_prepare,
.unprepare = clk_gate3_scu_unprepare,
.is_prepared = clk_gate3_scu_is_prepared,
static struct clk_ops clk_gate_scu_gpr_ops = {
.prepare = clk_gate_scu_gpr_prepare,
.unprepare = clk_gate_scu_gpr_unprepare,
.is_prepared = clk_gate_scu_gpr_is_prepared,
};
struct clk_hw *imx_clk_scu3(const char *name, const char *parent_name,
u32 rsrc_id, u8 gpr_id, bool invert_flag)
struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
u32 rsrc_id, u8 gpr_id, bool invert_flag)
{
struct clk_gate3_scu *gate;
struct clk_gate_gpr_scu *gate;
struct clk_hw *hw;
struct clk_init_data init;
int ret;
@ -445,7 +445,7 @@ struct clk_hw *imx_clk_scu3(const char *name, const char *parent_name,
if (gpr_id >= IMX_SC_C_LAST)
return NULL;
gate = kzalloc(sizeof(struct clk_gate3_scu), GFP_KERNEL);
gate = kzalloc(sizeof(struct clk_gate_gpr_scu), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
@ -455,7 +455,7 @@ struct clk_hw *imx_clk_scu3(const char *name, const char *parent_name,
gate->invert = invert_flag;
init.name = name;
init.ops = &clk_gate3_scu_ops;
init.ops = &clk_gate_scu_gpr_ops;
init.flags = 0;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;

2
drivers/clk/imx/clk-scu.h
View File

@ -63,7 +63,7 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
bit_idx, hw_gate);
}
struct clk_hw *imx_clk_scu3(const char *name, const char *parent_name,
struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
u32 rsrc_id, u8 gpr_id, bool invert_flag);
struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,