drm/i915: conditionally disable pch resources in ilk_crtc_disable
Simlar to how disable already works on haswell. This is possible since we now carefully track the pch state in the pipe config. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3436,7 +3436,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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intel_disable_planes(crtc);
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intel_disable_plane(dev_priv, plane, pipe);
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intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
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if (intel_crtc->config.has_pch_encoder)
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intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
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intel_disable_pipe(dev_priv, pipe);
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ironlake_pfit_disable(intel_crtc);
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@ -3445,43 +3447,46 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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if (encoder->post_disable)
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encoder->post_disable(encoder);
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ironlake_fdi_disable(crtc);
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if (intel_crtc->config.has_pch_encoder) {
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ironlake_fdi_disable(crtc);
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ironlake_disable_pch_transcoder(dev_priv, pipe);
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intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
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ironlake_disable_pch_transcoder(dev_priv, pipe);
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intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
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if (HAS_PCH_CPT(dev)) {
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/* disable TRANS_DP_CTL */
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reg = TRANS_DP_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
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temp |= TRANS_DP_PORT_SEL_NONE;
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I915_WRITE(reg, temp);
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if (HAS_PCH_CPT(dev)) {
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/* disable TRANS_DP_CTL */
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reg = TRANS_DP_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~(TRANS_DP_OUTPUT_ENABLE |
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TRANS_DP_PORT_SEL_MASK);
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temp |= TRANS_DP_PORT_SEL_NONE;
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I915_WRITE(reg, temp);
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/* disable DPLL_SEL */
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temp = I915_READ(PCH_DPLL_SEL);
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switch (pipe) {
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case 0:
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temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
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break;
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case 1:
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temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
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break;
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case 2:
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/* C shares PLL A or B */
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temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
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break;
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default:
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BUG(); /* wtf */
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/* disable DPLL_SEL */
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temp = I915_READ(PCH_DPLL_SEL);
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switch (pipe) {
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case 0:
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temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
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break;
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case 1:
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temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
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break;
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case 2:
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/* C shares PLL A or B */
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temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
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break;
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default:
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BUG(); /* wtf */
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}
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I915_WRITE(PCH_DPLL_SEL, temp);
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}
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I915_WRITE(PCH_DPLL_SEL, temp);
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/* disable PCH DPLL */
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intel_disable_pch_pll(intel_crtc);
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ironlake_fdi_pll_disable(intel_crtc);
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}
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/* disable PCH DPLL */
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intel_disable_pch_pll(intel_crtc);
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ironlake_fdi_pll_disable(intel_crtc);
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intel_crtc->active = false;
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intel_update_watermarks(dev);
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