pwm: Changes for v5.5-rc1
Various changes and minor fixes across a couple of drivers. -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl3ovpUZHHRoaWVycnku cmVkaW5nQGdtYWlsLmNvbQAKCRDdI6zXfz6zof9HD/9cawfrzpRp/wi/zt7BP2zk po/ttwso/9HsbhaEp8WyRBIeqTRh/D0BMT81UuaJZzus9qdcRycbwtoyKO1xnlWo LKHrpD/PvhJGjLGqEIymQm34o7hsvdwVGKkd2nisl2tNe2CNljcBO7DnnajM6qWX 0YaU6EE+SnZ/ApN6R3vF9IJZ+z8TJm2KLYHVupRxh0BDLGtbufNlpY7nTtOi1ADW ZaUTiVgEuJleGDwL+lNzdtWbzbBQGN/GnbpwutYJRsXuBNpYQNAS/WNOtZbi8BAv rxHPc4WLrqTm9yLgCgYY5SpjBZNbdN/liE7R0Lu5d4C3NleraSiTIHW5T5xnxitY PwShHszUIkKP4IadMLCbzlqRetcU6p3WNMivH7T6KHocTSCZDW0wmUs7YHrOLpfF EK6fJruRgcHdpPmMgPm0PAdKXeDSjkaCBDHms47A6JDsLnNYG8Oo0AyT9GFGdqz5 Sd0yOZeuUo+HSboJ19bZShfv+bAILdFqyiHfbZqzTBsKTqzBxEZXZKfWvnAgUCPh XisghxLlOtnUGD0Z2U22T0hTRNb7l/TCf8gRFL8X81qZnhxS9naXjdi5lvSuY+NA 6jw6N+GMwXUDmOYmN4HV9C39BNvUYzLoijYjUA/UPr3M2IKdX52hVhGo4B4gHVJB 0ylTmeN83Bf9fU7j3VkmHg== =Sd9F -----END PGP SIGNATURE----- Merge tag 'pwm/for-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "Various changes and minor fixes across a couple of drivers" * tag 'pwm/for-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: stm32: Pass breakinput instead of its values pwm: stm32: Remove clutter from ternary operator pwm: stm32: Validate breakinput data from DT pwm: Update comment on struct pwm_ops::apply pwm: sun4i: Fix incorrect calculation of duty_cycle/period pwm: stm32: Add power management support pwm: stm32: Split breakinput apply routine to ease PM support dt-bindings: pwm-stm32: Document pinctrl sleep state pwm: sun4i: Drop redundant assignment to variable pval dt-bindings: pwm: mediatek: Remove gratuitous compatible string for MT7629alistair/sunxi64-5.5-dsi
Linus Torvalds
commit
d9e48dc2a7
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@ -6,7 +6,7 @@ Required properties:
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- "mediatek,mt7622-pwm": found on mt7622 SoC.
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- "mediatek,mt7623-pwm": found on mt7623 SoC.
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- "mediatek,mt7628-pwm": found on mt7628 SoC.
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- "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC.
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- "mediatek,mt7629-pwm": found on mt7629 SoC.
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- "mediatek,mt8516-pwm": found on mt8516 SoC.
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- reg: physical base address and length of the controller's registers.
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- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
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@ -12,6 +12,7 @@
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#include <linux/mfd/stm32-timers.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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@ -19,6 +20,12 @@
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#define CCMR_CHANNEL_MASK 0xFF
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#define MAX_BREAKINPUT 2
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struct stm32_breakinput {
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u32 index;
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u32 level;
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u32 filter;
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};
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struct stm32_pwm {
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struct pwm_chip chip;
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struct mutex lock; /* protect pwm config/enable */
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@ -26,15 +33,11 @@ struct stm32_pwm {
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struct regmap *regmap;
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u32 max_arr;
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bool have_complementary_output;
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struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
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unsigned int num_breakinputs;
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u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
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};
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struct stm32_breakinput {
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u32 index;
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u32 level;
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u32 filter;
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};
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static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
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{
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return container_of(chip, struct stm32_pwm, chip);
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@ -488,22 +491,19 @@ static const struct pwm_ops stm32pwm_ops = {
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};
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static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
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int index, int level, int filter)
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const struct stm32_breakinput *bi)
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{
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u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E;
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int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT;
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u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF
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: TIM_BDTR_BK2E | TIM_BDTR_BK2P | TIM_BDTR_BK2F;
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u32 bdtr = bke;
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u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
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u32 bke = TIM_BDTR_BKE(bi->index);
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u32 bkp = TIM_BDTR_BKP(bi->index);
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u32 bkf = TIM_BDTR_BKF(bi->index);
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u32 mask = bkf | bkp | bke;
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u32 bdtr;
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/*
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* The both bits could be set since only one will be wrote
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* due to mask value.
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*/
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if (level)
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bdtr |= TIM_BDTR_BKP | TIM_BDTR_BK2P;
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bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
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bdtr |= (filter & TIM_BDTR_BKF_MASK) << shift;
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if (bi->level)
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bdtr |= bkp;
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regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
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@ -512,11 +512,25 @@ static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
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return (bdtr & bke) ? 0 : -EINVAL;
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}
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static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
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static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
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{
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unsigned int i;
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int ret;
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for (i = 0; i < priv->num_breakinputs; i++) {
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ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
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struct device_node *np)
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{
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struct stm32_breakinput breakinput[MAX_BREAKINPUT];
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int nb, ret, i, array_size;
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int nb, ret, array_size;
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unsigned int i;
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nb = of_property_count_elems_of_size(np, "st,breakinput",
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sizeof(struct stm32_breakinput));
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@ -531,20 +545,21 @@ static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
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if (nb > MAX_BREAKINPUT)
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return -EINVAL;
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priv->num_breakinputs = nb;
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array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
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ret = of_property_read_u32_array(np, "st,breakinput",
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(u32 *)breakinput, array_size);
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(u32 *)priv->breakinputs, array_size);
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if (ret)
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return ret;
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for (i = 0; i < nb && !ret; i++) {
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ret = stm32_pwm_set_breakinput(priv,
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breakinput[i].index,
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breakinput[i].level,
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breakinput[i].filter);
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for (i = 0; i < priv->num_breakinputs; i++) {
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if (priv->breakinputs[i].index > 1 ||
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priv->breakinputs[i].level > 1 ||
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priv->breakinputs[i].filter > 15)
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return -EINVAL;
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}
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return ret;
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return stm32_pwm_apply_breakinputs(priv);
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}
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static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
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@ -614,7 +629,7 @@ static int stm32_pwm_probe(struct platform_device *pdev)
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if (!priv->regmap || !priv->clk)
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return -EINVAL;
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ret = stm32_pwm_apply_breakinputs(priv, np);
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ret = stm32_pwm_probe_breakinputs(priv, np);
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if (ret)
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return ret;
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@ -647,6 +662,42 @@ static int stm32_pwm_remove(struct platform_device *pdev)
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return 0;
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}
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static int __maybe_unused stm32_pwm_suspend(struct device *dev)
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{
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struct stm32_pwm *priv = dev_get_drvdata(dev);
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unsigned int i;
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u32 ccer, mask;
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/* Look for active channels */
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ccer = active_channels(priv);
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for (i = 0; i < priv->chip.npwm; i++) {
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mask = TIM_CCER_CC1E << (i * 4);
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if (ccer & mask) {
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dev_err(dev, "PWM %u still in use by consumer %s\n",
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i, priv->chip.pwms[i].label);
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return -EBUSY;
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}
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}
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return pinctrl_pm_select_sleep_state(dev);
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}
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static int __maybe_unused stm32_pwm_resume(struct device *dev)
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{
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struct stm32_pwm *priv = dev_get_drvdata(dev);
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int ret;
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ret = pinctrl_pm_select_default_state(dev);
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if (ret)
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return ret;
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/* restore breakinput registers that may have been lost in low power */
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return stm32_pwm_apply_breakinputs(priv);
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}
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static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
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static const struct of_device_id stm32_pwm_of_match[] = {
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{ .compatible = "st,stm32-pwm", },
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{ /* end node */ },
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@ -659,6 +710,7 @@ static struct platform_driver stm32_pwm_driver = {
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.driver = {
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.name = "stm32-pwm",
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.of_match_table = stm32_pwm_of_match,
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.pm = &stm32_pwm_pm_ops,
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},
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};
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module_platform_driver(stm32_pwm_driver);
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@ -137,10 +137,10 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
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tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
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tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
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tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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}
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@ -156,7 +156,6 @@ static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
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if (sun4i_pwm->data->has_prescaler_bypass) {
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/* First, test without any prescaler when available */
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prescaler = PWM_PRESCAL_MASK;
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pval = 1;
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/*
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* When not using any prescaler, the clock period in nanoseconds
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* is not an integer so round it half up instead of
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@ -70,14 +70,11 @@
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#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
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#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
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#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
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#define TIM_BDTR_BKE BIT(12) /* Break input enable */
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#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
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#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
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#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
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#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
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#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
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#define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19))
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#define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23))
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#define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */
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#define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */
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#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
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#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
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#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
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@ -87,8 +84,7 @@
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#define TIM_CR2_MMS2_SHIFT 20
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#define TIM_SMCR_TS_SHIFT 4
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#define TIM_BDTR_BKF_MASK 0xF
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#define TIM_BDTR_BKF_SHIFT 16
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#define TIM_BDTR_BK2F_SHIFT 20
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#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
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enum stm32_timers_dmas {
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STM32_TIMERS_DMA_CH1,
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@ -243,10 +243,7 @@ pwm_set_relative_duty_cycle(struct pwm_state *state, unsigned int duty_cycle,
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* @request: optional hook for requesting a PWM
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* @free: optional hook for freeing a PWM
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* @capture: capture and report PWM signal
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* @apply: atomically apply a new PWM config. The state argument
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* should be adjusted with the real hardware config (if the
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* approximate the period or duty_cycle value, state should
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* reflect it)
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* @apply: atomically apply a new PWM config
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* @get_state: get the current PWM state. This function is only
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* called once per PWM device when the PWM chip is
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* registered.
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Reference in New Issue