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mmc: tmio: refactor CLK_CTL bit calculation 

for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
          clock <<= 1;

... is too tricky, hence I replaced with

  roundup_pow_of_two(divisor) >> 2

'(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but
it is not clear.  'divisor <= 1' is easier to understand.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
hifive-unleashed-5.1
Masahiro Yamada 2018-08-23 13:44:20 +09:00 committed by Ulf Hansson
parent 68f83127fe
commit db4cea918e
1 changed files with 13 additions and 5 deletions
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18
drivers/mmc/host/tmio_mmc.c
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@ -45,19 +45,27 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
unsigned int new_clock)
{
u32 clk = 0, clock;
unsigned int clock, divisor;
u32 clk = 0;
int clk_sel;
if (new_clock == 0) {
tmio_mmc_clk_stop(host);
return;
}
clock = host->mmc->f_min;
divisor = host->pdata->hclk / new_clock;
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
clock <<= 1;
if (divisor <= 1) {
clk_sel = 1;
clk = 0;
} else {
clk_sel = 0;
/* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
clk = roundup_pow_of_two(divisor) >> 2;
}
host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1);
host->pdata->set_clk_div(host->pdev, clk_sel);
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));