clk: AST2600: Add mux for EMMC clock
[ Upstream commit5.4-rM2-2.2.x-imx-squashedc2407ab3bd
] The EMMC clock can be derived from either the HPLL or the MPLL. Register a clock mux so that the rate is calculated correctly based upon the parent. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20200709195706.12741-2-eajames@linux.ibm.com Acked-by: Joel Stanley <joel@jms.id.au> Fixes:d3d04f6c33
("clk: Add support for AST2600 SoC") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
parent
0392f18139
commit
dc92d84b37
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@ -130,6 +130,18 @@ static const struct clk_div_table ast2600_eclk_div_table[] = {
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{ 0 }
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{ 0 }
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};
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};
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static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
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{ 0x0, 2 },
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{ 0x1, 4 },
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{ 0x2, 6 },
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{ 0x3, 8 },
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{ 0x4, 10 },
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{ 0x5, 12 },
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{ 0x6, 14 },
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{ 0x7, 16 },
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{ 0 }
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};
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static const struct clk_div_table ast2600_mac_div_table[] = {
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static const struct clk_div_table ast2600_mac_div_table[] = {
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{ 0x0, 4 },
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{ 0x0, 4 },
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{ 0x1, 4 },
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{ 0x1, 4 },
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@ -389,6 +401,11 @@ static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
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return hw;
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return hw;
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}
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}
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static const char *const emmc_extclk_parent_names[] = {
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"emmc_extclk_hpll_in",
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"mpll",
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};
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static const char * const vclk_parent_names[] = {
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static const char * const vclk_parent_names[] = {
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"dpll",
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"dpll",
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"d1pll",
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"d1pll",
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@ -458,16 +475,32 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
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return PTR_ERR(hw);
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return PTR_ERR(hw);
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aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
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aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
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/* EMMC ext clock divider */
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/* EMMC ext clock */
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hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
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hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
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scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
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0, 1, 2);
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&aspeed_g6_clk_lock);
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if (IS_ERR(hw))
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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return PTR_ERR(hw);
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hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
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scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
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hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
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ast2600_div_table,
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emmc_extclk_parent_names,
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&aspeed_g6_clk_lock);
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ARRAY_SIZE(emmc_extclk_parent_names), 0,
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scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
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0, &aspeed_g6_clk_lock);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
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0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
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15, 0, &aspeed_g6_clk_lock);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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hw = clk_hw_register_divider_table(dev, "emmc_extclk",
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"emmc_extclk_gate", 0,
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scu_g6_base +
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ASPEED_G6_CLK_SELECTION1, 12,
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3, 0, ast2600_emmc_extclk_div_table,
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&aspeed_g6_clk_lock);
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if (IS_ERR(hw))
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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return PTR_ERR(hw);
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aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
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aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
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