[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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@ -105,7 +105,7 @@ etrap_save: save %g2, -STACK_BIAS, %sp
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/* Go to trap time globals so we can save them. */
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661: wrpr %g0, ETRAP_PSTATE1, %pstate
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.section .gl_1insn_patch, "ax"
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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SET_GL(0)
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.previous
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@ -206,7 +206,7 @@ etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
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wrpr %g0, 1, %tl
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661: nop
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.section .gl_1insn_patch, "ax"
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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SET_GL(1)
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.previous
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@ -67,7 +67,7 @@ kvmap_itlb_longpath:
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -179,7 +179,7 @@ kvmap_dtlb_longpath:
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -234,7 +234,7 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
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/* Normal globals are restored, go to trap globals. */
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661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
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.section .gl_1insn_patch, "ax"
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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SET_GL(1)
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.previous
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@ -316,7 +316,7 @@ user_rtt_fill_fixup:
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wrpr %g0, RTRAP_PSTATE, %pstate
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661: nop
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.section .gl_1insn_patch, "ax"
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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SET_GL(0)
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.previous
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@ -549,16 +549,16 @@ static void __init per_cpu_patch(void)
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#endif
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}
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static void __init gl_patch(void)
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static void __init sun4v_patch(void)
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{
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struct gl_1insn_patch_entry *p1;
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struct gl_2insn_patch_entry *p2;
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struct sun4v_1insn_patch_entry *p1;
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struct sun4v_2insn_patch_entry *p2;
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if (tlb_type != hypervisor)
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return;
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p1 = &__gl_1insn_patch;
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while (p1 < &__gl_1insn_patch_end) {
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p1 = &__sun4v_1insn_patch;
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while (p1 < &__sun4v_1insn_patch_end) {
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unsigned long addr = p1->addr;
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*(unsigned int *) (addr + 0) = p1->insn;
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@ -568,8 +568,8 @@ static void __init gl_patch(void)
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p1++;
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}
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p2 = &__gl_2insn_patch;
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while (p2 < &__gl_2insn_patch_end) {
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p2 = &__sun4v_2insn_patch;
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while (p2 < &__sun4v_2insn_patch_end) {
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unsigned long addr = p2->addr;
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*(unsigned int *) (addr + 0) = p2->insns[0];
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@ -606,7 +606,7 @@ void __init setup_arch(char **cmdline_p)
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*/
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per_cpu_patch();
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gl_patch();
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sun4v_patch();
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boot_flags_init(*cmdline_p);
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@ -74,7 +74,7 @@ tsb_dtlb_load:
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661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
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retry
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -99,7 +99,7 @@ tsb_itlb_load:
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661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -130,7 +130,7 @@ tsb_do_fault:
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -145,7 +145,7 @@ tsb_do_dtlb_fault:
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661: mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov %g4, %g5
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nop
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@ -250,7 +250,7 @@ __tsb_context_switch:
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661: mov TSB_REG, %g1
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stxa %o1, [%g1] ASI_DMMU
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov SCRATCHPAD_UTSBREG1, %g1
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stxa %o1, [%g1] ASI_SCRATCHPAD
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@ -260,7 +260,7 @@ __tsb_context_switch:
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661: stxa %o1, [%g1] ASI_IMMU
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membar #Sync
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -80,12 +80,12 @@ SECTIONS
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__cpuid_patch = .;
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.cpuid_patch : { *(.cpuid_patch) }
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__cpuid_patch_end = .;
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__gl_1insn_patch = .;
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.gl_1insn_patch : { *(.gl_1insn_patch) }
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__gl_1insn_patch_end = .;
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__gl_2insn_patch = .;
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.gl_2insn_patch : { *(.gl_2insn_patch) }
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__gl_2insn_patch_end = .;
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__sun4v_1insn_patch = .;
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.sun4v_1insn_patch : { *(.sun4v_1insn_patch) }
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__sun4v_1insn_patch_end = .;
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__sun4v_2insn_patch = .;
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.sun4v_2insn_patch : { *(.sun4v_2insn_patch) }
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__sun4v_2insn_patch_end = .;
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. = ALIGN(8192);
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__initramfs_start = .;
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.init.ramfs : { *(.init.ramfs) }
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@ -447,7 +447,7 @@ xcall_sync_tick:
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661: rdpr %pstate, %g2
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wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -478,7 +478,7 @@ xcall_report_regs:
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661: rdpr %pstate, %g2
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wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
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.section .gl_2insn_patch, "ax"
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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@ -78,17 +78,20 @@ struct cpuid_patch_entry {
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extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
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#endif
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struct gl_1insn_patch_entry {
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struct sun4v_1insn_patch_entry {
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unsigned int addr;
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unsigned int insn;
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};
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extern struct gl_1insn_patch_entry __gl_1insn_patch, __gl_1insn_patch_end;
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extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
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__sun4v_1insn_patch_end;
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struct gl_2insn_patch_entry {
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struct sun4v_2insn_patch_entry {
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unsigned int addr;
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unsigned int insns[2];
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};
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extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
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extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
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__sun4v_2insn_patch_end;
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#endif /* !(__ASSEMBLY__) */
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#define TRAP_PER_CPU_THREAD 0x00
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