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arm64: imx8-ss-dc0/1.dtsi: Add common dpu clocks 

Currently, all DPUs in i.MX8qm/qxp have the same clocks - pll0/1,
bypass0 and disp0/1.  So add the common clocks in imx8-ss-dc0/1.dtsi.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Liu Ying 2019-08-08 13:06:11 +08:00 committed by Dong Aisheng
parent ef80f59c77
commit ed49c29a99
4 changed files with 12 additions and 15 deletions
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6
arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
View File

@ -269,6 +269,12 @@ dc0_subsys: bus@56000000 {
"framegen1_primsync_off",
"framegen1_secsync_on",
"framegen1_secsync_off";
clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1";
power-domains = <&pd IMX_SC_R_DC_0>,
<&pd IMX_SC_R_DC_0_PLL_0>,
<&pd IMX_SC_R_DC_0_PLL_1>;

6
arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi
View File

@ -270,6 +270,12 @@ dc1_subsys: bus@57000000 {
"framegen1_primsync_off",
"framegen1_secsync_on",
"framegen1_secsync_off";
clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_1_VIDEO0 IMX_SC_PM_CLK_BYPASS>,
<&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>;
clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1";
power-domains = <&pd IMX_SC_R_DC_1>,
<&pd IMX_SC_R_DC_1_PLL_0>,
<&pd IMX_SC_R_DC_1_PLL_1>;

10
arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi
View File

@ -6,11 +6,6 @@
&dpu1 {
compatible = "fsl,imx8qm-dpu";
clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
clock-names = "pll0", "pll1", "disp0", "disp1";
dpu1_disp0: port@0 {
reg = <0>;
@ -31,11 +26,6 @@
&dpu2 {
compatible = "fsl,imx8qm-dpu";
clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>;
clock-names = "pll0", "pll1", "disp0", "disp1";
dpu2_disp0: port@0 {
reg = <0>;

5
arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
View File

@ -6,11 +6,6 @@
&dpu1 {
compatible = "fsl,imx8qxp-dpu";
clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
clock-names = "pll0", "pll1", "disp0", "disp1";
dpu_disp0: port@0 {
reg = <0>;