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clk: imx6sl: configure epdc clock to get desired value 

configure epdc clock to get desired value

Signed-off-by: Robby Cai <robby.cai@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Robby Cai 2019-09-06 21:54:10 -04:00 committed by Dong Aisheng
parent 6dd9caaf69
commit f84e37af2c
1 changed files with 10 additions and 0 deletions
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10
drivers/clk/imx/clk-imx6sl.c
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@ -430,10 +430,20 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* Audio-related clocks configuration */
clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk);
/* Initialize Video PLLs to valid frequency (650MHz). */
clk_set_rate(hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk, 650000000);
/* set PLL5 video as lcdif pix parent clock */
clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk,
hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);
/* Configure EPDC clocks */
clk_set_parent(hws[IMX6SL_CLK_EPDC_PIX_SEL]->clk,
hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);
clk_set_parent(hws[IMX6SL_CLK_EPDC_AXI_SEL]->clk,
hws[IMX6SL_CLK_PLL2_PFD2]->clk);
clk_set_rate(hws[IMX6SL_CLK_EPDC_AXI]->clk, 200000000);
clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
hws[IMX6SL_CLK_PLL2_PFD2]->clk);