QE: remove PPCisms for QE
QE was supported on PowerPC, and dependent on PPC, Now it is supported on other platforms. so remove PPCisms. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>5.4-rM2-2.2.x-imx-squashed
Zhao Qiang
Dong Aisheng
parent
6318feef83
commit
ffc21ad04e
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@ -5,7 +5,7 @@
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config QUICC_ENGINE
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bool "QUICC Engine (QE) framework support"
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depends on FSL_SOC && PPC32
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depends on OF && HAS_IOMEM
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select GENERIC_ALLOCATOR
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select CRC32
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help
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@ -30,8 +30,6 @@
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#include <asm/pgtable.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#include <asm/prom.h>
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#include <asm/rheap.h>
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static void qe_snums_init(void);
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static int qe_sdma_init(void);
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@ -104,15 +102,27 @@ void qe_reset(void)
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panic("sdma init failed!");
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}
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/* issue commands to QE, return 0 on success while -EIO on error
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*
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* @cmd: the command code, should be QE_INIT_TX_RX, QE_STOP_TX and so on
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* @device: which sub-block will run the command, QE_CR_SUBBLOCK_UCCFAST1 - 8
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* , QE_CR_SUBBLOCK_UCCSLOW1 - 8, QE_CR_SUBBLOCK_MCC1 - 3,
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* QE_CR_SUBBLOCK_IDMA1 - 4 and such on.
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* @mcn_protocol: specifies mode for the command for non-MCC, should be
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* QE_CR_PROTOCOL_HDLC_TRANSPARENT, QE_CR_PROTOCOL_QMC, QE_CR_PROTOCOL_UART
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* and such on.
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* @cmd_input: command related data.
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*/
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int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
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{
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unsigned long flags;
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u8 mcn_shift = 0, dev_shift = 0;
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u32 ret;
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int ret;
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int i;
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spin_lock_irqsave(&qe_lock, flags);
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if (cmd == QE_RESET) {
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out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
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iowrite32be((cmd | QE_CR_FLG), &qe_immr->cp.cecr);
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} else {
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if (cmd == QE_ASSIGN_PAGE) {
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/* Here device is the SNUM, not sub-block */
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@ -129,20 +139,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
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mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
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}
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out_be32(&qe_immr->cp.cecdr, cmd_input);
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out_be32(&qe_immr->cp.cecr,
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(cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
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mcn_protocol << mcn_shift));
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iowrite32be(cmd_input, &qe_immr->cp.cecdr);
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iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) |
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(u32)mcn_protocol << mcn_shift), &qe_immr->cp.cecr);
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}
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/* wait for the QE_CR_FLG to clear */
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ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
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100, 0);
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ret = -EIO;
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for (i = 0; i < 100; i++) {
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if ((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0) {
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ret = 0;
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break;
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}
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udelay(1);
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}
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/* On timeout (e.g. failure), the expression will be false (ret == 0),
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otherwise it will be true (ret == 1). */
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spin_unlock_irqrestore(&qe_lock, flags);
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return ret == 1;
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return ret;
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}
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EXPORT_SYMBOL(qe_issue_cmd);
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@ -167,6 +183,8 @@ unsigned int qe_get_brg_clk(void)
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int size;
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const u32 *prop;
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unsigned int mod;
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u32 val;
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int ret;
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if (brg_clk)
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return brg_clk;
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@ -175,9 +193,9 @@ unsigned int qe_get_brg_clk(void)
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if (!qe)
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return brg_clk;
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prop = of_get_property(qe, "brg-frequency", &size);
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if (prop && size == sizeof(*prop))
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brg_clk = *prop;
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ret = of_property_read_u32(qe, "brg-frequency", &val);
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if (!ret)
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brg_clk = val;
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of_node_put(qe);
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@ -223,14 +241,16 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
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/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
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that the BRG divisor must be even if you're not using divide-by-16
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mode. */
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#ifdef CONFIG_PPC
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if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
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if (!div16 && (divisor & 1) && (divisor > 3))
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divisor++;
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#endif
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tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
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QE_BRGC_ENABLE | div16;
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out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
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iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
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return 0;
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}
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@ -377,9 +397,9 @@ static int qe_sdma_init(void)
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return -ENOMEM;
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}
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out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
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out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
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(0x1 << QE_SDMR_CEN_SHIFT)));
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iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK, &sdma->sdebcr);
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iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
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&sdma->sdmr);
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return 0;
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}
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@ -417,14 +437,14 @@ static void qe_upload_microcode(const void *base,
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"uploading microcode '%s'\n", ucode->id);
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/* Use auto-increment */
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out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
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QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
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iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE |
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QE_IRAM_IADD_BADDR, &qe_immr->iram.iadd);
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for (i = 0; i < be32_to_cpu(ucode->count); i++)
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out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
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iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
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/* Set I-RAM Ready Register */
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out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
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iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
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}
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/*
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@ -509,7 +529,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
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* If the microcode calls for it, split the I-RAM.
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*/
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if (!firmware->split)
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setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
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qe_setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
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if (firmware->soc.model)
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printk(KERN_INFO
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@ -543,11 +563,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
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u32 trap = be32_to_cpu(ucode->traps[j]);
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if (trap)
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out_be32(&qe_immr->rsp[i].tibcr[j], trap);
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iowrite32be(trap, &qe_immr->rsp[i].tibcr[j]);
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}
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/* Enable traps */
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out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
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iowrite32be(be32_to_cpu(ucode->eccr), &qe_immr->rsp[i].eccr);
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}
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qe_firmware_uploaded = 1;
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@ -18,8 +18,6 @@
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#include <asm/io.h>
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#include <soc/fsl/qe/qe.h>
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#include <asm/prom.h>
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#include <sysdev/fsl_soc.h>
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#undef DEBUG
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@ -57,16 +55,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
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pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
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/* Set open drain, if required */
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tmp_val = in_be32(&par_io->cpodr);
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tmp_val = ioread32be(&par_io->cpodr);
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if (open_drain)
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out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
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iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
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else
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out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
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iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
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/* define direction */
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tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
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in_be32(&par_io->cpdir2) :
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in_be32(&par_io->cpdir1);
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ioread32be(&par_io->cpdir2) :
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ioread32be(&par_io->cpdir1);
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/* get all bits mask for 2 bit per port */
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pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
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@ -78,34 +76,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
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/* clear and set 2 bits mask */
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if (pin > (QE_PIO_PINS / 2) - 1) {
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out_be32(&par_io->cpdir2,
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~pin_mask2bits & tmp_val);
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iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
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tmp_val &= ~pin_mask2bits;
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out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
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iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
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} else {
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out_be32(&par_io->cpdir1,
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~pin_mask2bits & tmp_val);
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iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
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tmp_val &= ~pin_mask2bits;
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out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
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iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
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}
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/* define pin assignment */
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tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
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in_be32(&par_io->cppar2) :
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in_be32(&par_io->cppar1);
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ioread32be(&par_io->cppar2) :
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ioread32be(&par_io->cppar1);
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new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
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(pin % (QE_PIO_PINS / 2) + 1) * 2));
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/* clear and set 2 bits mask */
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if (pin > (QE_PIO_PINS / 2) - 1) {
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out_be32(&par_io->cppar2,
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~pin_mask2bits & tmp_val);
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iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
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tmp_val &= ~pin_mask2bits;
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out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
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iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
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} else {
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out_be32(&par_io->cppar1,
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~pin_mask2bits & tmp_val);
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iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
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tmp_val &= ~pin_mask2bits;
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out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
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iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
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}
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}
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EXPORT_SYMBOL(__par_io_config_pin);
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@ -133,12 +127,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
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/* calculate pin location */
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pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
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tmp_val = in_be32(&par_io[port].cpdata);
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tmp_val = ioread32be(&par_io[port].cpdata);
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if (val == 0) /* clear */
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out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
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iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
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else /* set */
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out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
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iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
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return 0;
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}
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@ -169,10 +169,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
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&siram[siram_entry_id * 32 + 0x200 + i]);
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}
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setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
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SIR_LAST);
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setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
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SIR_LAST);
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qe_setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
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SIR_LAST);
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qe_setbits16(&siram[(siram_entry_id * 32) + 0x200 +
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(utdm->num_of_ts - 1)], SIR_LAST);
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/* Set SIxMR register */
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sixmr = SIMR_SAD(siram_entry_id);
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@ -35,7 +35,7 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
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return -EINVAL;
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spin_lock_irqsave(&cmxgcr_lock, flags);
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clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
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qe_clrsetbits32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
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ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
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spin_unlock_irqrestore(&cmxgcr_lock, flags);
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@ -80,7 +80,7 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
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return -EINVAL;
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}
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clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
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qe_clrsetbits8(guemr, UCC_GUEMR_MODE_MASK,
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UCC_GUEMR_SET_RESERVED3 | speed);
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return 0;
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@ -109,9 +109,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
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get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
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if (set)
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setbits32(cmxucr, mask << shift);
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qe_setbits32(cmxucr, mask << shift);
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else
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clrbits32(cmxucr, mask << shift);
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qe_clrbits32(cmxucr, mask << shift);
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return 0;
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}
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@ -207,7 +207,7 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
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if (mode == COMM_DIR_RX)
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shift += 4;
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clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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qe_clrsetbits32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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clock_bits << shift);
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return 0;
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@ -29,41 +29,41 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
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printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
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printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
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&uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
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printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
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&uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
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printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
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&uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
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printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
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&uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
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printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
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&uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
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printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
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&uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
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printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
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&uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
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&uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
|
||||
printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
|
||||
&uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
|
||||
&uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
|
||||
printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
|
||||
&uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
|
||||
&uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
|
||||
printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
|
||||
&uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
|
||||
&uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
|
||||
printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
|
||||
&uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
|
||||
&uccf->uf_regs->urfset, ioread16be(&uccf->uf_regs->urfset));
|
||||
printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
|
||||
&uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
|
||||
&uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
|
||||
printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
|
||||
&uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
|
||||
&uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
|
||||
printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
|
||||
&uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
|
||||
&uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
|
||||
printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
|
||||
&uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
|
||||
&uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
|
||||
printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
|
||||
&uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
|
||||
&uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
|
||||
printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
|
||||
&uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
|
||||
&uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
|
||||
printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
|
||||
&uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
|
||||
&uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
|
||||
}
|
||||
EXPORT_SYMBOL(ucc_fast_dump_regs);
|
||||
|
||||
|
|
@ -85,7 +85,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
|
|||
|
||||
void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
|
||||
{
|
||||
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
|
||||
iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
|
||||
}
|
||||
EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
|
||||
|
||||
|
|
@ -97,7 +97,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
|
|||
uf_regs = uccf->uf_regs;
|
||||
|
||||
/* Enable reception and/or transmission on this UCC. */
|
||||
gumr = in_be32(&uf_regs->gumr);
|
||||
gumr = ioread32be(&uf_regs->gumr);
|
||||
if (mode & COMM_DIR_TX) {
|
||||
gumr |= UCC_FAST_GUMR_ENT;
|
||||
uccf->enabled_tx = 1;
|
||||
|
|
@ -106,7 +106,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
|
|||
gumr |= UCC_FAST_GUMR_ENR;
|
||||
uccf->enabled_rx = 1;
|
||||
}
|
||||
out_be32(&uf_regs->gumr, gumr);
|
||||
iowrite32be(gumr, &uf_regs->gumr);
|
||||
}
|
||||
EXPORT_SYMBOL(ucc_fast_enable);
|
||||
|
||||
|
|
@ -118,7 +118,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
|
|||
uf_regs = uccf->uf_regs;
|
||||
|
||||
/* Disable reception and/or transmission on this UCC. */
|
||||
gumr = in_be32(&uf_regs->gumr);
|
||||
gumr = ioread32be(&uf_regs->gumr);
|
||||
if (mode & COMM_DIR_TX) {
|
||||
gumr &= ~UCC_FAST_GUMR_ENT;
|
||||
uccf->enabled_tx = 0;
|
||||
|
|
@ -127,7 +127,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
|
|||
gumr &= ~UCC_FAST_GUMR_ENR;
|
||||
uccf->enabled_rx = 0;
|
||||
}
|
||||
out_be32(&uf_regs->gumr, gumr);
|
||||
iowrite32be(gumr, &uf_regs->gumr);
|
||||
}
|
||||
EXPORT_SYMBOL(ucc_fast_disable);
|
||||
|
||||
|
|
@ -259,12 +259,13 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
|
|||
gumr |= uf_info->tenc;
|
||||
gumr |= uf_info->tcrc;
|
||||
gumr |= uf_info->mode;
|
||||
out_be32(&uf_regs->gumr, gumr);
|
||||
iowrite32be(gumr, &uf_regs->gumr);
|
||||
|
||||
/* Allocate memory for Tx Virtual Fifo */
|
||||
uccf->ucc_fast_tx_virtual_fifo_base_offset =
|
||||
qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
|
||||
if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
|
||||
if (IS_ERR_VALUE((unsigned long)uccf->
|
||||
ucc_fast_tx_virtual_fifo_base_offset)) {
|
||||
printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
|
||||
__func__);
|
||||
uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
|
||||
|
|
@ -277,7 +278,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
|
|||
qe_muram_alloc(uf_info->urfs +
|
||||
UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
|
||||
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
|
||||
if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
|
||||
if (IS_ERR_VALUE((unsigned long)uccf->
|
||||
ucc_fast_rx_virtual_fifo_base_offset)) {
|
||||
printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
|
||||
__func__);
|
||||
uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
|
||||
|
|
@ -286,15 +288,15 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
|
|||
}
|
||||
|
||||
/* Set Virtual Fifo registers */
|
||||
out_be16(&uf_regs->urfs, uf_info->urfs);
|
||||
out_be16(&uf_regs->urfet, uf_info->urfet);
|
||||
out_be16(&uf_regs->urfset, uf_info->urfset);
|
||||
out_be16(&uf_regs->utfs, uf_info->utfs);
|
||||
out_be16(&uf_regs->utfet, uf_info->utfet);
|
||||
out_be16(&uf_regs->utftt, uf_info->utftt);
|
||||
iowrite16be(uf_info->urfs, &uf_regs->urfs);
|
||||
iowrite16be(uf_info->urfet, &uf_regs->urfet);
|
||||
iowrite16be(uf_info->urfset, &uf_regs->urfset);
|
||||
iowrite16be(uf_info->utfs, &uf_regs->utfs);
|
||||
iowrite16be(uf_info->utfet, &uf_regs->utfet);
|
||||
iowrite16be(uf_info->utftt, &uf_regs->utftt);
|
||||
/* utfb, urfb are offsets from MURAM base */
|
||||
out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
|
||||
out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
|
||||
iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
|
||||
iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
|
||||
|
||||
/* Mux clocking */
|
||||
/* Grant Support */
|
||||
|
|
@ -362,14 +364,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
|
|||
}
|
||||
|
||||
/* Set interrupt mask register at UCC level. */
|
||||
out_be32(&uf_regs->uccm, uf_info->uccm_mask);
|
||||
iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
|
||||
|
||||
/* First, clear anything pending at UCC level,
|
||||
* otherwise, old garbage may come through
|
||||
* as soon as the dam is opened. */
|
||||
|
||||
/* Writing '1' clears */
|
||||
out_be32(&uf_regs->ucce, 0xffffffff);
|
||||
iowrite32be(0xffffffff, &uf_regs->ucce);
|
||||
|
||||
*uccf_ret = uccf;
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include <soc/fsl/qe/ucc_slow.h>
|
||||
|
||||
#include <linux/firmware.h>
|
||||
#include <asm/cpm.h>
|
||||
#include <asm/reg.h>
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <asm/cpm.h>
|
||||
#include <soc/fsl/qe/immap_qe.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue