commit a1158e36f8 upstream.
It is found on many allwinner soc that there is a low probability that
the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This
will cause the interrupt status of a gpio bank to always be active on
gic, preventing gic from responding to other spi interrupts correctly.
So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/85263ce8b058e80cea25c6ad6383eb256ce96cc8.1604988979.git.frank@allwinnertech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.
Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).
This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:
commit 402bfb3c13 ("Support I/O bias voltage setting on A80")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
H6 has a different I/O voltage bias setting method than A80. Prepare
existing code for using alternative bias voltage setting methods.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Our pin controller can configure the pins no matter how they are muxed, so
it makes sense to allow this for GPIOs as well.
Add the generic set_config function so that we can rely on the existing
pinctrl code we have.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Lines are usually ended with a semi-column in C, yet this was copied from a
structure declaration to the init variant while keeping the comma at the
end. Make sure we have a normal syntax, instead of multiple assignments.
Fixes: d83c82ce7c ("pinctrl: sunxi: support multiple pin controller")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sunxi pinctrl only implements the pin_config_group_set callback at the
moment, whereas the gpiochip_generic_config function relies on
pin_config_set. Rework the functions a little to support pin_config_set,
and rely on it for pin_config_group_set.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A80 SoC has configuration registers for I/O bias voltage. Incorrect
settings would make the affected peripherals inoperable in some cases,
such as Ethernet RGMII signals biased at 2.5V with the settings still
at 3.3V. However low speed signals such as MDIO on the same group of
pins seem to be unaffected.
Previously there was no way to know what the actual voltage used was,
short of hard-coding a value in the device tree. With the new pin bank
regulator supply support in place, the driver can now query the
regulator for its voltage, and if it's valid (as opposed to being the
dummy regulator), set the bias voltage setting accordingly.
Add a quirk to denote the presence of the configuration registers, and
a function to set the correct setting based on the voltage read back
from the regulator.
This is only done when the regulator is first acquired and enabled.
While it would be nice to have a notifier on the regulator so that when
the voltage changes, the driver can update the setting, in practice no
board currently supports dynamic changing of the I/O voltages.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On most newer Allwinner SoCs, there are two pinctrl devices, the PIO and
R_PIO. PIO covers pin-banks PA to PI (PJ and PK have not been seen),
while R_PIO covers PL to PN. The regulator array only has space for 12
entries, which was designed to cover PA to PL. On the A80, the pin banks
go up to PN, which would be the 14th entry in the regulator array.
However since the driver only needs to track regulators for its own pin
banks, the array only needs to have 9 entries, and also take in to
account the value of pin_base, such that the regulator for the first
pin-bank of the pinctrl device, be it "PA" or "PL" uses the first entry
of the array.
Base the regulator array index on pin_base, such that "PA" for PIO and
"PL" for R_PIO both take the first element within their respective
device's regulator array.
Also decrease the size of the regulator array to 9, just enough to cover
"PA" to "PI".
Fixes: 9a2a566adb ("pinctrl: sunxi: Deal with per-bank regulators")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The new per-pin-bank regulator handling code in the sunxi pinctrl driver
has mismatched conditions for enabling and disabling the regulator: it
is enabled each time a pin is requested, but only disabled when the
pin-bank's reference count reaches zero.
Since we are doing reference counting already, there's no need to enable
the regulator each time a pin is requested. Instead we can just do it
for the first requested pin of each pin-bank. Thus we can reverse the
test and bail out early if it's not the first occurrence.
Fixes: 9a2a566adb ("pinctrl: sunxi: Deal with per-bank regulators")
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Allwinner SoCs have on most of their GPIO banks a regulator input.
This issue was mainly ignored so far because either the regulator was a
static regulator that would be providing power anyway, or the bank was used
for a feature unsupported so far (CSI). For the odd cases, enabling it in
the bootloader was the preferred option.
However, now that we are starting to support those features, and that we
can't really rely on the bootloader for this, we need to model those
regulators as such in the DT.
This is slightly more complicated than what it looks like, since some
regulators will be tied to the PMIC, and in order to have access to the
PMIC bus, you need to mux its pins, which will need the pinctrl driver,
that needs the regulator driver to be registered. And this is how you get a
circular dependency.
In practice however, the hardware cannot fall into this case since it would
result in a completely unusable bus. In order to avoid that circular
dependency, we can thus get and enable the regulators at pin_request time.
We'll then need to account for the references of all the pins of a
particular branch to know when to put the reference, but it works pretty
nicely once implemented.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If 'krealloc()' fails, 'pctl->functions' is set to NULL.
We should instead use a temp variable in order to be able to free the
previously allocated memeory, in case of OOM.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
fixes following Smatch static check warning:
./drivers/pinctrl/sunxi/pinctrl-sunxi.c:1112 sunxi_pinctrl_build_state()
warn: passing devm_ allocated variable to kfree. 'pctrl->functions'
As we will be calling krealloc() on pointer 'pctrl->functions', which means
kfree() will be called in there, devm_kzalloc() shouldn't be used with
the allocation in the first place. Fix the warning by calling kcalloc()
and managing the free procedure in error path on our own.
Fixes: 0e37f88d9a ("ARM: sunxi: Add pinctrl driver for Allwinner SoCs")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A new open coder has crept in since 470b73a384 ("pinctrl: sunxi:
Use of_clk_get_parent_count() instead of open coding"), replace it.
of_clk_get_parent_count() was moved to <linux/of_clk.h>, so include that
instead of <linux/clk-provider.h>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
As the new H6 SoC has holes in the IRQ registers, refactor the IRQ
related register function for getting the full pinctrl desc structure.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Allwinner pinctrl device tree binding suggests that a clock named
"apb" would drive the pin controller IP. However (for legacy reasons) we
rely on this clock actually being the first clock defined.
Since named clocks can be in any order, let's explicitly check for a
clock called "apb" if there is more than one clock referenced.
Kudo to Maxime for suggesting this much more elegant approach.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pin function can not be match correctly when SUNXI_PIN describe with
mutiple variant and same function.
such as:
on pinctrl-sun4i-a10.c
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */
PINCTRL_SUN8I_R40)),
it would always match to the first variant function
(PINCTRL_SUN4I_A10, PINCTRL_SUN7I_A20)
so we should add variant compare on it.
Signed-off-by: hao_zhang <hao5781286@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The strict mode should always have been enabled on our driver, and leaving
it unchecked just makes it harder to find a migration path as time passes.
Let's enable it by default now so that hopefully the new SoCs should be
safe.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Our pinctrl device should have had strict set all along. However, it wasn't
the case, and most of our old device trees also have a pinctrl group in
addition to the GPIOs properties, which mean that we can't really turn it
on now.
All our new SoCs don't have that group, so we should still enable that mode
on the newer one though.
In order to enable it by default, add a flag that will allow to disable
that mode that should be set by pinctrl drivers that cannot be migrated.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This reverts commit 2154d94b40.
The original patch was intented to avoid some issues with the sunxi
gpio rework and was supposed to be reverted after all the required
DT bits had been merged around v4.10.
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
struct irq_domain_ops is not modified, so it can be made const.
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sunxi pinctrl driver currently implement an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel. Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.
A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.
Signed-off-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Switch the generic pin config argument from 16 to 24 bits,
only use 8 bits for the configuration type. We might need to
encode more information about a certain setting than we need
to encode different generic settings.
- Add a cross-talk API to the pin control GPIO back-end,
utilizing pinctrl_gpio_set_config() from GPIO drivers that
want to set up a certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the
GPIO chips, so that they pass a generic configuration for
things like debouncing and single ended (typically open
drain). This change has also been merged in an immutable
branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing
a pin controller before trying to get any hogs.
- For pin controllers putting all group and function definitions
into the device tree, we now have generic code to deal with
this and it is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down.
New subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in
the LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on
GPIOs. Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode.
STM32H743 MCU support.
- Allwinner sunxi: deep simplifications on how to support
subvariants of SoCs without adding to much SoC-specific data
for each subvariant, especially for sun5i variants. New driver
for V3s SoCs. New driver for the H5 SoC. Support A31/A31s
variants with the new variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction.
New subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the
SoC driver to access regmaps. Add infrastructure for pin-bank
retention control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly
in the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm
driver realtime-safe.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJYq/7kAAoJEEEQszewGV1zf4oQALVaN5tuaCbzN4QOq87jzXmk
K195kKG0nkNvN6o5llNhBszHfCSmX1+oSscxuCF/88kH4mFHeDIbvg0KOk5IZYxA
YlT8NA75C9+flARE3gQUyL320ulahWbvOthntQprzsVU4RJa0zP38peQsfiUd8W1
ch8GInJYYkczcsAbmziyUOBu5a2o9tX3u8BF8FaBf2uyrCiBC/ZT2VpzvbOR5NeU
MvjFvc7bq2fNltzDNHdZZUo/5iCbnPlRNig2umDp5fFa8rZcdPmGMAOl4p6nizHY
S16xDl38xxDQx8sp1IH4n+th3G2cXoONEj9eZ6woWTJhLbLc13CacYPfleYfqEOe
+JyrUgBgFBINiFWDHHaebWJeD2M/QF4FnSDGnnJBy/bKWe6lJnknGvSZNcIEvdvB
QeeKyfrvnKiCyjNY4N+ZNdMLA2vj5o86vG2hSqztPiwYWDePbN76yeZ7l79bFfOo
ZnCa2ay70Np7xwrQWors4Gl2LV2zJG7AkaNA7vvS9NX6OURu/SkNVePkY1XHCLwu
lNvYd4iwFJxzXm08TsgtLC080eZfvCot9xqbgzvoapnwx7tBuaAakXI4bh0T3x4n
pEauKO3oNE/K89mN9QK2jfsD9kDWvm4xvc+ilA6DGU0C37XnDQjF+Q5xy16262Gh
9w0yWMlqzrr7stUXAjS4
=IMY0
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Pin control bulk changes for the v4.11 kernel cycle.
Core changes:
- Switch the generic pin config argument from 16 to 24 bits, only use
8 bits for the configuration type. We might need to encode more
information about a certain setting than we need to encode
different generic settings.
- Add a cross-talk API to the pin control GPIO back-end, utilizing
pinctrl_gpio_set_config() from GPIO drivers that want to set up a
certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the GPIO chips,
so that they pass a generic configuration for things like
debouncing and single ended (typically open drain). This change has
also been merged in an immutable branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing a pin
controller before trying to get any hogs.
- For pin controllers putting all group and function definitions into
the device tree, we now have generic code to deal with this and it
is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down. New
subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in the
LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on GPIOs.
Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode. STM32H743 MCU
support.
- Allwinner sunxi: deep simplifications on how to support subvariants
of SoCs without adding to much SoC-specific data for each
subvariant, especially for sun5i variants. New driver for V3s SoCs.
New driver for the H5 SoC. Support A31/A31s variants with the new
variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction. New
subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the SoC
driver to access regmaps. Add infrastructure for pin-bank retention
control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly in
the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm driver
realtime-safe"
* tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (111 commits)
pinctrl: samsung: Fix return value check in samsung_pinctrl_get_soc_data()
pinctrl: intel: unlock on error in intel_config_set_pull()
pinctrl: berlin: make bool drivers explicitly non-modular
pinctrl: spear: make bool drivers explicitly non-modular
pinctrl: mvebu: make bool drivers explicitly non-modular
pinctrl: sunxi: make sun5i explicitly non-modular
pinctrl: sunxi: Remove stray printk call in sun5i driver's probe function
pinctrl: samsung: mark PM functions as __maybe_unused
pinctrl: sunxi: Remove redundant A31s pinctrl driver
pinctrl: sunxi: Support A31/A31s with pinctrl variants
pinctrl: Amend bindings for STM32 pinctrl
pinctrl: Add STM32 pinctrl driver DT bindings
pinctrl: stm32: Add STM32H743 MCU support
include: dt-bindings: Add STM32H7 pinctrl DT defines
gpio: aspeed: Remove dependence on GPIOF_* macros
pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
drivers: pinctrl: add driver for Allwinner H5 SoC
pinctrl: intel: Add Intel Gemini Lake pin controller support
pinctrl: intel: Add support for 1k additional pull-down
pinctrl: intel: Add support for hardware debouncer
...
Commit 07fe64ba21 ("pinctrl: sunxi: Handle bias disable") actually
enforced enforced the disabling of the pull up/down resistors instead of
ignoring it like it was done before.
This was part of a wider rework to switch to the generic pinconf bindings,
and was meant to be merged together with DT patches that were switching to
it, and removing what was considered default values by both the binding and
the boards. This included no bias on a pin.
However, those DT patches were delayed to 4.11, which would be fine only
for a significant number boards having the bias setup wrong, which in turns
break the MMC on those boards (and possibly other devices too).
In order to avoid conflicts as much as possible, bring back the old
behaviour for 4.10, and we'll revert that commit once all the DT bits will
have landed.
Tested-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The current pinconf packed format allows only 16-bit argument limiting
the maximum value 65535. For most types this is enough. However,
debounce time can be in range of hundreths of milliseconds in case of
mechanical switches so we cannot represent the worst case using the
current format.
In order to support larger values change the packed format so that the
lower 8 bits are used as type which leaves 24 bits for the argument.
This allows representing values up to 16777215 and debounce times up to
16 seconds.
We also convert the existing users to use 32-bit integer when extracting
argument from the packed configuration value.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some SoCs are either supposed to be pin compatible (A10 and A20 for
example), or are just repackaged versions of the same die (A10s, A13, GR8).
In those case, having a full blown pinctrl driver just introduces
duplication in both data size and maintainance effort.
Add a variant option to both pins and functions to be able to limit the
pins and functions described only to a subset of the SoC we support with a
given driver.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Smatch complains that we dereference "map" before testing it for NULL
which is true. We should be testing "*map" instead. Also on the error
path, we should free *map and set it to NULL.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
gcc warns about a way that it could use an uninitialized variable:
drivers/pinctrl/sunxi/pinctrl-sunxi.c: In function 'sunxi_pinctrl_init':
drivers/pinctrl/sunxi/pinctrl-sunxi.c:1191:8: error: 'best_div' may be used uninitialized in this function [-Werror=maybe-uninitialized]
This cannot really happen except if 'freq' is UINT_MAX and 'clock' is
zero, and both of these are forbidden. To shut up the warning anyway,
this changes the logic to initialize the return code to the first
divider value before looking at the others.
Fixes: 7c926492d3 ("pinctrl: sunxi: Add support for interrupt debouncing")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin controller found in the Allwinner SoCs has support for interrupts
debouncing.
However, this is not done per-pin, preventing us from using the generic
pinconf binding for that, but per irq bank, which, depending on the SoC,
ranges from one to five.
Introduce a device-wide property to deal with this using a microsecond
resolution. We can re-use the per-pin input-debounce property for that, so
let's do it!
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sunxi_pconf_reg helper introduced in the last patch gives us the
chance to rework sunxi_pconf_group_set to have it match the structure
of sunxi_pconf_(group_)get and make it easier to understand.
For each config to set, it:
1. checks if the parameter is supported.
2. checks if the argument is within limits.
3. converts argument to the register value.
4. writes to the register with spinlock held.
As a result the function now blocks unsupported config parameters,
instead of silently ignoring them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sunxi pinctrl driver only caches whatever pinconf setting was last
set on a given pingroup. This is not particularly helpful, nor is it
correct.
Fix this by actually reading the hardware registers and returning
the correct results or error codes. Also filter out unsupported
pinconf settings. Since this driver has a peculiar setup of 1 pin
per group, we can support both pin and pingroup pinconf setting
read back with the same code. The sunxi_pconf_reg helper and code
structure is inspired by pinctrl-msm.
With this done we can also claim to support generic pinconf, by
setting .is_generic = true in pinconf_ops.
Also remove the cached config value. The behavior of this was never
correct, as it only cached 1 setting instead of all of them. Since
we can now read back settings directly from the hardware, it is no
longer required.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
According to pinconf-generic.h, the argument for
PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled
with a pull up/down resistor, zero if it is directly connected
to VDD or ground.
Since Allwinner hardware uses a weak pull resistor internally,
the argument should be 1.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In the recently refactored sunxi pinctrl library, we are only allocating
one set of pin configs for each pinmux setting node. When the pinctrl_map
structure is freed, the pin configs should also be freed. However the
code assumed the first map would contain the configs, which actually
never happens, as the mux function map gets added first.
The proper way to do this is to look through all the maps and free the
first one whose type is actually PIN_MAP_TYPE_CONFIGS_GROUP.
Also slightly expand the comment explaining this.
Fixes: f233dbca62 ("pinctrl: sunxi: Rework the pin config building code")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Even though the our binding had the assumption that the allwinner,pull and
allwinner,drive properties were optional, the code never took that into
account.
Fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Our bindings are mostly irrelevant now that we have generic pinctrl
bindings that cover exactly the same uses cases.
Add support for the new ones, and obviously keep our old binding support in
order to keep the ABI stable.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
So far, putting NO_PULL in allwinner,pull was ignored, behaving like if
that property was not there at all.
Obviously, this is not the right thing to do, and in that case, we really
need to just disable the bias.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since we have some bindings header for our hardcoded flags, let's use them
when we can.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to support more easily the generic pinctrl properties, rework the
pinctrl maps configuration and split it into several sub-functions.
One of the side-effects from that rework is that we only parse the pin
configuration once, since it's going to be common to every pin, instead of
having to parsing once for each pin.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The generic GPIO library directly implement code for acpi_find_gpio()
which is only used with CONFIG_ACPI. This was probably done because
OF did the same thing, but I removed that so remove this too.
Rename the internal acpi_find_gpio() in gpiolib-acpi.c to
acpi_populate_gpio_lookup() which seems to be more appropriate anyway
so as to avoid a namespace clash with the same function.
Make the stub return -ENOENT rather than -ENOSYS (as that is for
syscalls!).
For some reason the sunxi pin control driver was including the private
gpiolib header, it works just fine without it so remove that oneliner.
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Add the devm_pinctrl_register() API and switch all applicable drivers
to use it, saving lots of lines of code all over the place.
New drivers:
- New driver for the Broadcom NS2 SoC.
- New subdriver for the PXA25x SoCs.
- New subdriver for the AMLogic Meson GXBB SoC.
Driver improvements:
- The Intel Baytrail driver now properly supports pin control.
- The Nomadik, Rockchip, Broadcom BCM2835 supports the .get_direction() callback in
the GPIO portions.
- Continued development and stabilization of several SH-PFC
SoC subdrivers: r8a7795, r8a7790, r8a7794 etc.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXPZ9PAAoJEEEQszewGV1zboIQALtGX/tyKFzaOsj7WxHHjmfb
yufqU62NE0sPT6/hzUY3a1U9dpakbMehBXy0go0vcShmPSznX2glFv4GR6LEeE0+
o0JNv0d13f2s5WPEqn6L/ePuSuNNjfkwjZ7YJlAXx/WqAWI9c70H8/VHsXEObWOe
ZsAZx2FdUFDOxugDWsCmU6kt7RXbqTzEz2M/dDANr4B2cRH/3yny797P2y9tLy3w
Rqsdqw1C1A9SICSIRZ+YBWctXhRq5APsB75IncUYIQJF5hXoAcBCp6v+cNZHpXOw
X9J+zKDeMjOSsVvOyHA+4P+vPYgkOPl9GuUVJRvnbfCZYKEhDM1e5F393Cf7gYYz
dIEAzIFlPmZCMxog7AWEA0yDp2rJ2W/5WoN7pg+a5cKSHgriIry1sxDslBD2b9ZW
XxdVm4pMOiVw6yokHI4g2hcDsZOEW8zhPQi1wPuVuJ3k1m7T/d13mFAFTSWwOLVx
WFDLuD20ybkCVmxEs0ePrDzLcgEnxW40src6lqSzIx8bUBCH+iWPkIPH0fAJ6bNK
TFtfcCFrtE2YmpxrCgZceTLER/7jAGkXFegbJq1epNmz7+0wbEbRxcVFE1IbYUBW
ejslgTtLDvnzzkR7UISZF/Qna066tCGT52sEA82ZcrqytGkSTLB4kUDkQvXaCB0r
4DLJ47K32mQu3MrOPLjE
=tlvn
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This kernel cycle was quite calm when it comes to pin control and
there is really just one major change, and that is the introduction of
devm_pinctrl_register() managed resources.
Apart from that linear development, details below.
Core changes:
- Add the devm_pinctrl_register() API and switch all applicable
drivers to use it, saving lots of lines of code all over the place.
New drivers:
- driver for the Broadcom NS2 SoC
- subdriver for the PXA25x SoCs
- subdriver for the AMLogic Meson GXBB SoC
Driver improvements:
- the Intel Baytrail driver now properly supports pin control
- Nomadik, Rockchip, Broadcom BCM2835 support the .get_direction()
callback in the GPIO portions
- continued development and stabilization of several SH-PFC SoC
subdrivers: r8a7795, r8a7790, r8a7794 etc"
* tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (85 commits)
Revert "pinctrl: tegra: avoid parked_reg and parked_bank"
pinctrl: meson: Fix eth_tx_en bit index
pinctrl: tegra: avoid parked_reg and parked_bank
pinctrl: tegra: Correctly check the supported configuration
pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC
pinctrl: rockchip: fix pull setting error for rk3399
pinctrl: stm32: Implement .pin_config_dbg_show()
pinctrl: nomadik: hide nmk_gpio_get_mode when unused
pinctrl: ns2: rename pinctrl_utils_dt_free_map
pinctrl: at91: Merge clk_prepare and clk_enable into clk_prepare_enable
pinctrl: at91: Make at91_gpio_template const
pinctrl: baytrail: fix some error handling in debugfs
pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC
pinctrl: sirf/atlas7: trivial fix of spelling mistake on flagged
pinctrl: sh-pfc: Kill unused variable in sh_pfc_remove()
pinctrl: nomadik: implement .get_direction()
pinctrl: nomadik: use BIT() with offsets consequently
pinctrl: exynos5440: Use off-stack memory for pinctrl_gpio_range
pinctrl: zynq: Use devm_pinctrl_register() for pinctrl registration
pinctrl: u300: Use devm_pinctrl_register() for pinctrl registration
...
Use devm_pinctrl_register() for pin control registration and clean
the error path.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl-sun8i-a33.c (and the dts) declare only 2 interrupt banks,
where as the closely related a23 has 3 banks. This matches with the
datasheet for the A33 where only interrupt banks B and G are specified
where as the A23 has banks A, B and G.
However the A33 being the A23 derative it is means that the interrupt
configure/status io-addresses for the 2 banks it has are not changed
from the A23, iow they have the same address as if bank A was still
present. Where as the sunxi pinctrl currently tries to use the A23 bank
A addresses for bank B, since the pinctrl code does not know about the
removed bank A.
Add a irq_bank_base parameter and use this where appropriate to take
the missing bank A into account.
This fixes external interrupts not working on the A33 (tested with
an i2c touchscreen controller which uses an external interrupt).
Cc: stable@vger.kernel.org
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- The gpio_chip is now a *real device*. Until now the gpio chips
were just piggybacking the parent device or (gasp) floating in
space outside of the device model. We now finally make GPIO chips
devices. The gpio_chip will create a gpio_device which contains
a struct device, and this gpio_device struct is kept private.
Anything that needs to be kept private from the rest of the kernel
will gradually be moved over to the gpio_device.
- As a result of making the gpio_device a real device, we have added
resource management, so devm_gpiochip_add_data() will cut down on
overhead and reduce code lines. A huge slew of patches convert
almost all drivers in the subsystem to use this.
- Building on making the GPIO a real device, we add the first step
of a new userspace ABI: the GPIO character device. We take small
steps here, so we first add a pure *information* ABI and the tool
"lsgpio" that will list all GPIO devices on the system and all
lines on these devices. We can now discover GPIOs properly from
userspace. We still have not come up with a way to actually *use*
GPIOs from userspace.
- To encourage people to use the character device for the future,
we have it always-enabled when using GPIO. The old sysfs ABI is
still opt-in (and can be used in parallel), but is marked as
deprecated. We will keep it around for the foreseeable future,
but it will not be extended to cover ever more use cases.
Cleanup:
- Bjorn Helgaas removed a whole slew of per-architecture <asm/gpio.h>
includes. This dates back to when GPIO was an opt-in feature and
no shared library even existed: just a header file with proper
prototypes was provided and all semantics were up to the arch to
implement. These patches make the GPIO chip even more a proper
device and cleans out leftovers of the old in-kernel API here
and there. Still some cruft is left but it's very little now.
- There is still some clamping of return values for .get() going
on, but we now return sane values in the vast majority of drivers
and the errorpath is sanitized. Some patches for powerpc, blackfin
and unicore still drop in.
- We continue to switch the ARM, MIPS, blackfin, m68k local GPIO
implementations to use gpiochip_add_data() and cut down on code
lines.
- MPC8xxx is converted to use the generic GPIO helpers.
- ATH79 is converted to use the generic GPIO helpers.
New drivers:
- WinSystems WS16C48
- Acces 104-DIO-48E
- F81866 (a F7188x variant)
- Qoric (a MPC8xxx variant)
- TS-4800
- SPI serializers (pisosr): simple 74xx shift registers connected
to SPI to obtain a dirt-cheap output-only GPIO expander.
- Texas Instruments TPIC2810
- Texas Instruments TPS65218
- Texas Instruments TPS65912
- X-Gene (ARM64) standby GPIO controller
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJW6m24AAoJEEEQszewGV1zUasP/RpTrjRcNI5QFHjudd2oioDx
R/IljC06Q072ZqVy/MR7QxwhoU8jUnCgKgv4rgMa1OcfHblxC2R1+YBKOUSij831
E+SYmYDYmoMhN7j5Aslr66MXg1rLdFSdCZWemuyNruAK8bx6cTE1AWS8AELQzzTn
Re/CPpCDbujLy0ZK2wJHgr9ZkdcBGICtDRCrOR3Kyjpwk/DSZcruK1PDN+VQMI3k
bJlwgtGenOHINgCq/16edpwj/hzmoJXhTOZXJHI5XVR6czTwb3SvCYACvCkauI/a
/N7b3quG88b5y0OPQPVxp5+VVl9GyVcv5oGzIfTNat/g5QinShZIT4kVV9r0xu6/
TQHh1HlXleh+QI3yX0oRv9ztHreMf+vdpw1dhIwLqHqfJ7AWdOGk7BbKjwCrsOoq
t/qUVFnyvooLpyr53Z5JY8+LqyynHF68G+jUQyHLgTZ0GCE+z+1jqNl1T501n3kv
3CSlNYxSN/YUBN3cnroAIU/ZWcV4YRdxmOtEWP+7xgcdzTE6s/JHb2fuEfVHzWPf
mHWtJGy8U0IR4VSSEln5RtjhRr0PAjTHeTOGAmivUnaIGDziTowyUVF+X5hwC77E
DGTuLVx/Kniv173DK7xNAsUZNAETBa3fQZTgu+RfOpMiM1FZc7tI1rd7K7PjbyCc
d2M0gcq+d11ITJTxC7OM
=9AJ4
-----END PGP SIGNATURE-----
Merge tag 'gpio-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for kernel v4.6. There is quite a
lot of interesting stuff going on.
The patches to other subsystems and arch-wide are ACKed as far as
possible, though I consider things like per-arch <asm/gpio.h> as
essentially a part of the GPIO subsystem so it should not be needed.
Core changes:
- The gpio_chip is now a *real device*. Until now the gpio chips
were just piggybacking the parent device or (gasp) floating in
space outside of the device model.
We now finally make GPIO chips devices. The gpio_chip will create
a gpio_device which contains a struct device, and this gpio_device
struct is kept private. Anything that needs to be kept private
from the rest of the kernel will gradually be moved over to the
gpio_device.
- As a result of making the gpio_device a real device, we have added
resource management, so devm_gpiochip_add_data() will cut down on
overhead and reduce code lines. A huge slew of patches convert
almost all drivers in the subsystem to use this.
- Building on making the GPIO a real device, we add the first step of
a new userspace ABI: the GPIO character device. We take small
steps here, so we first add a pure *information* ABI and the tool
"lsgpio" that will list all GPIO devices on the system and all
lines on these devices.
We can now discover GPIOs properly from userspace. We still have
not come up with a way to actually *use* GPIOs from userspace.
- To encourage people to use the character device for the future, we
have it always-enabled when using GPIO. The old sysfs ABI is still
opt-in (and can be used in parallel), but is marked as deprecated.
We will keep it around for the foreseeable future, but it will not
be extended to cover ever more use cases.
Cleanup:
- Bjorn Helgaas removed a whole slew of per-architecture <asm/gpio.h>
includes.
This dates back to when GPIO was an opt-in feature and no shared
library even existed: just a header file with proper prototypes was
provided and all semantics were up to the arch to implement. These
patches make the GPIO chip even more a proper device and cleans out
leftovers of the old in-kernel API here and there.
Still some cruft is left but it's very little now.
- There is still some clamping of return values for .get() going on,
but we now return sane values in the vast majority of drivers and
the errorpath is sanitized. Some patches for powerpc, blackfin and
unicore still drop in.
- We continue to switch the ARM, MIPS, blackfin, m68k local GPIO
implementations to use gpiochip_add_data() and cut down on code
lines.
- MPC8xxx is converted to use the generic GPIO helpers.
- ATH79 is converted to use the generic GPIO helpers.
New drivers:
- WinSystems WS16C48
- Acces 104-DIO-48E
- F81866 (a F7188x variant)
- Qoric (a MPC8xxx variant)
- TS-4800
- SPI serializers (pisosr): simple 74xx shift registers connected to
SPI to obtain a dirt-cheap output-only GPIO expander.
- Texas Instruments TPIC2810
- Texas Instruments TPS65218
- Texas Instruments TPS65912
- X-Gene (ARM64) standby GPIO controller"
* tag 'gpio-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (194 commits)
Revert "Share upstreaming patches"
gpio: mcp23s08: Fix clearing of interrupt.
gpiolib: Fix comment referring to gpio_*() in gpiod_*()
gpio: pca953x: Fix pca953x_gpio_set_multiple() on 64-bit
gpio: xgene: Fix kconfig for standby GIPO contoller
gpio: Add generic serializer DT binding
gpio: uapi: use 0xB4 as ioctl() major
gpio: tps65912: fix bad merge
Revert "gpio: lp3943: Drop pin_used and lp3943_gpio_request/lp3943_gpio_free"
gpio: omap: drop dev field from gpio_bank structure
gpio: mpc8xxx: Slightly update the code for better readability
gpio: mpc8xxx: Remove *read_reg and *write_reg from struct mpc8xxx_gpio_chip
gpio: mpc8xxx: Fixup setting gpio direction output
gpio: mcp23s08: Add support for mcp23s18
dt-bindings: gpio: altera: Fix altr,interrupt-type property
gpio: add driver for MEN 16Z127 GPIO controller
gpio: lp3943: Drop pin_used and lp3943_gpio_request/lp3943_gpio_free
gpio: timberdale: Switch to devm_ioremap_resource()
gpio: ts4800: Add IMX51 dependency
gpiolib: rewrite gpiodev_add_to_list
...
This file is not modular, nor is it using modular functions. The
only thing close is the global THIS_MODULE which comes from export.h
so lets replace it appropriately and cut back on the amount of
header stuff we draw in by several thousand lines.
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This kind of hacks disturbs the refactoring of the gpiolib.
The descriptor table belongs to the gpiolib, if we want to know
something about something in it, use or define the proper accessor
functions. Let's add this gpiochip_lins_is_irq() to do what the
sunxi driver is trying at so we can privatize the descriptors
properly.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Yangtao Li