SLSLICE[2] cannot be accessed on 8DXL platform since it is
fixed and locked clock, but can be accessed on 8qm/8qxp platforms
who want to assign the clock to 250Mhz.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Align i.MX 8mm Job ring node naming
with the rest of the i.MX 8 platforms.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Align i.MX 8QXP/QM Job ring node naming
with the rest of the i.MX 8 platforms.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
There is a shared gate clock exists after 'IMX8MP_CLK_MEDIA_
AXI_ROOT' and 'IMX8MP_CLK_MEDIA_AXI_ROOT' clocks according to
the clock tree, so correct clock values for 'mediamix-pd' by
using the corresponding gate clocks.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
The GPU3D shader clock must be on to make sure that GPU3D can be reset
successfully.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
correct property name. power-active-high
USB OTG2 power pin function set problem is fixed by scfw
848498bf4c6d79b33cc5018969574a5369479bc4
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Commit 729dcffd1e ("usb: dwc3: gadget: Add support for disabling
U1 and U2 entries") give detail explaination for user case of
disable u1 and u2 in gadget mode:
"Usecase 1:
When combining dwc3 with an redriver for a USB Type-C device
solution, itsometimes have problems with leaving U1/U2 for
certain hosts, resulting in link training errors and reconnects.
For this U1/U2 state entries may be avoided."
on imx8mq-evk board, we have typec and redriver used and android
reported unstable issue when use some host PC for adb, so to have
a better performance, we disable u1 and u2 entries.
Reported-by: Richard Liu <xuegang.liu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
dai-index property must match dai-index from topology. FSL DAI
driver uses it for now figure out the correct DAI name, but might
be used for other things in the future.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
With the reserved memory for optee, Linux is no
longer able to allocate CMA within the allocation
range defined in the dtb.
Increase the alloc-range so that Linux can allocate in the 4G
address range (in case some DMA are not able to address more).
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
Correct the HDMI irqsteer's interrupt controller parent, otherwise the HDMI
irq can NOT wakeup the cpu core from idle timely, then HDMI performance
will be impacted.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
IC confirmed the both imx8qm and imx8qxp could use 250M as usb3_clk
and no performance drop.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Add new compatible 'imx8mp-sdma' for sdma2/sdma3 to support resume back after
audiomix off.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Topology is similar with the one for i.MX8QXP but now we really
use correct name for SAI: sai3 instead of sai1.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The GPU AXI/AHB & ML AXI/AHB clock must be on when doing corresponding
power domain on/off, so Add these clocks to GPUMIX & MLMIX power domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
With GPC as interrupt parent, need set edac and irqsteer interrupt
parent as gpc.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
iMX8DXL EVK board only has 1GB DDR, so it can't allocate 960MB CMA.
Change the CMA size to 320M to align with 8DX.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
The MIPI clock parenting is made in dts file, causing the MIPI clocks to
be parented even if that specific MIPI node is needed or not, causing
issues to the LVDS block (which has a shared PHY with MIPI on 8QXP).
In order to avoid these problems with the shared PHY on 8QXP, store the
MIPI parent clock for phy and escape clocks, along with their rates and
do the re-parenting in the MIPI driver only when a bridge (or panel) is
attached to it.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
[Aisheng: Tested on MX8QM/QXP with single LVDS-HDMI or MIPI panel]
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 2f794bb2f88e18e43dab31f2edea98177fce4e95)
A new device tree file fsl-ls1028a-rdb-dpdk.dts is added
for user space networking.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Li Yang <leoyang.li@nxp.com>
(cherry picked from commit 5c1ec7a8a42de9b144ee87177c016270a3334492)
Now seems only ls1028a-qds using overlay by adding fragment dtbs.
Add their support in Makefile.
This is one of approach suggested by DT maintainer Rob here:
https://lore.kernel.org/patchwork/patch/821645/
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 7220fa2e1a02e471f5d3276601709f3df372ee63)
Labels are used to name switch port net devices in Linux, use more
convenient names to make it simpler for users.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 3ad82375cfc4d4f6df68ebe02164995de654001c)
Adds overlays for various serdes protocols on LS1028A QDS board using
different PHY cards. These should be applied at boot, based on serdes
configuration. If no overlay is applied, only the RGMII interface on
the QDS is available in Linux.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 779c69e4ae9d1535e958cda7309f030293e3c45c)
Named the ports node of the Felix Eth switch so it can be used in DT
overlays to associate the ports with proper PHYs.
Ports are now by default disabled in dtsi, so if the board dts doesn't
do anything about them they stay disabled.
Updated RDB and QDS dts files to match.
Replaced all 'phy-connection-type' with 'phy-mode'.
The set-up for protocol 7777 on QDS was changed to a single quad port card
in slot 1. This requires a QDS board with no lane B rework and a AQR412
or similar PHY card without any lane rework done on it.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 0462421755cb92b3ee9ace632d15a9a19db9f14c)
Use ethernet-phy@ADDR, previously the numbers were wrong.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 4085dc853441dd17b53a95d19f324d76d946fee3)
This was missed when moving the CPU port and disabling eno3.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit b180bb294ef127e40f11d186443aed162cd5d270)
This enables monitoring of link status and AN. It should also physically
enable SGMII AN with the VSC8514 PHY, but in practice that is still
hardcoded as "on" in the PHY driver, at the moment. So since Felix
actually disables SGMII AN when this DT property is absent, this would
result in an in-band AN mismatch between the MAC and the PHY. So this
property is required for the moment for this MAC/PHY combination.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit 57575d3b92a1b2ca9fb0e75dcf20d8283df2dcfd)
This reverts commit 841edb9867.
There are 2 separate issues with interrupts on the LS1028A-RDB board:
1. The GPIO1_DAT25 interrupt line is shared, so there is a real risk of
race conditions if used in edge-triggered mode, as we currently do.
This can be illustrated in the following setup:
- Take 2 LS1028A-RDB boards
- Connect swp0 to swp0, swp1 to swp1, swp2 to swp2
- Plug/unplug the power to board 2, 10 times in a row. This will make
the PHYs lose link simultaneously.
- Notice that at one point, the net devices on board 1 remain in a
state where not all the links are down (visible in "ip link"):
5: swp0: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:70 brd ff:ff:ff:ff:ff:ff
6: swp1: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:71 brd ff:ff:ff:ff:ff:ff
7: swp2: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state DOWN mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:72 brd ff:ff:ff:ff:ff:ff
This cannot be solved by making the interrupts level-triggered,
because the gpio-mpc8xxx controller only supports generating
edge-triggered interrupts. So the effective reality is that we
cannot not use shared interrupts connected to the gpio1
interrupt-parent.
2. The uBUS1 and uBUS2 slots that share this interrupt line with the
Ethernet PHYs are not pulled up by default, they are left floating on
current revisions of the LS1028A-RDB boards. So sufficient electrical
noise on these lines will make the CPLD think there's an interrupt
request, so it asserts the GPIO1_DAT25 signal and leaves it asserted.
This means that the PHYs on those boards will never have link when
used in interrupt mode, because their IRQ will be masked by the uBUS
line that is erroneously kept asserted. In poll mode this issue does
not occur.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit f0d8d28ed417194f9e83e495949225d18d1505c7)
Use generic node name and specific label name.
Add m25p,fast-read.
Use dt-bindings constants in interrupts instead of using numbers.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit 58f10e679079d68275f961f131bb146abf532b6d)
Use compatibles as "jedec,spi-nor" to probe flash without displaying
warning: found s25fs512s, expected m25p80.
Remove "fsl,qspi-has-second-chip" as new driver doesn't use it anymore.
Update rx and tx width to 1.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit 538bebe00be17f49d6f4c5b5b75be67ba4bf6ed4)
Use compatibles as "jedec,spi-nor" to probe flash without displaying
warning: found s25fs512s, expected m25p80.
Also remove "fsl,qspi-has-second-chip" property as new driver doesn't use
it anymore.
Update dtsi compatibles to use "fsl,ls2080a-qspi".
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit 7afe154e046717c9c6249ac7ded256563236811a)
Add the iommu-map property to the pci nodes so that the firmware
fixes it up with the required values thus enabling iommu for
devices connected over pci.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
(cherry picked from commit 94db63e57e5150e693ab39a3195a0ac02000fb05)
Decrease the maximum allowed memory bandwidth for the LCDIF-ADV7535
use-case. The reason for this decrease is described by errata e11326.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 3fb1a1b1065be60b06540de066a737244c97fb86)
The eDMA of LS1028A soc has a little bit different from others, So we
should distinguish them in driver by compatible.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
(cherry picked from commit fa6956d853b3ebed26e1588e7b78d959701fa841)
remove the redundant qspi node in i.MX8MQ EVK dts
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 55983f692e8cff1c0892dfb7d3c5b7fa2a2341b4)
Update rx and tx bus-width to 1.
Use compatibles as "jedec,spi-nor" to probe flash without displaying warning:
found s25fs512s, expected m25p80
Remove property 'big-endian' as it is not used by new driver anymore.
Also, update dtsi compatibles to use "fsl,ls1021a-qspi".
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit e9f44d4f413bc6b8cd0d9fdaece2bcc1cb1edbc5)
According to latest datasheet Rev.0.1, 03/2020, VDD_ARM does
NOT have dependency on VDD_SOC, so below table in datasheet
can be used directly for VDD_ARM:
Clock Voltage
1.2GHz 0.85V
1.4GHz 0.95V
1.5GHz 1.0V
For DDR4 EVK board, system runs at nominal mode, so GPU can
ONLY run up to 400MHz.
For LPDDR4 EVK board, system runs at over-drive mode, so GPU
can run up to 600MHz.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Jason Liu