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7 Commits (4343f61103cdb8ccd6f3d5dd7168f1176a1cee37)

Author SHA1 Message Date
Kamal Dasu a5f2246fb9 dt: bindings: mtd: replace references to nand.txt with nand-controller.yaml
nand-controller.yaml replaced nand.txt however the references to it were
not updated. This change updates these references wherever it appears in
bindings documentation.

Fixes: 212e496935 ("dt-bindings: mtd: Add YAML schemas for the generic NAND options")
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2019-05-22 09:08:20 -05:00
Abhishek Sahu c168ac273c dt-bindings: qcom_nandc: update for ECC strength and step size
1. If nand-ecc-strength specified in DT, then controller will use
   this ECC strength otherwise ECC strength will be calculated
   according to chip requirement and available OOB size.

2. QCOM NAND controller supports only one step size (512 bytes) but
   nand-ecc-step-size is required property in DT. This DT property
   can be removed and ecc step size can be assigned in driver with
   512 bytes value.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-07-18 09:24:05 +02:00
Abhishek Sahu d440c4d360 dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation
Qualcom IPQ8074 SoC uses QPIC NAND controller version 1.5.0
which uses BAM DMA Engine.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-08-23 16:49:30 +02:00
Abhishek Sahu ec170cc853 dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation
1. Qualcom IPQ4019 SoC uses QPIC NAND controller version 1.4.0
   which uses BAM DMA Engine while IPQ806x uses EBI2 NAND
   which uses ADM DMA Engine.
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
   while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
   BAM DMA.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-08-23 16:49:30 +02:00
Abhishek Sahu 24d8735708 dt-bindings: qcom_nandc: fix the ipq806x device tree example
1. Correct the compatible string for IPQ806x
2. Change the NAND controller and NAND chip nodes name
   for more clarity.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-08-23 16:49:29 +02:00
Abhishek Sahu 4d4f212136 dt-bindings: qcom_nandc: remove chip select compatible string
Currently the compatible “qcom,nandcs” is being used for each
connected NAND device to support for multiple NAND devices in the
same bus. The same thing can be achieved by looking reg property
for each sub nodes which contains the chip select number so this
patch removes the use of “qcom,nandcs” for specifying NAND device
sub nodes.

Since there is no user for this driver currently in so
changing compatible string is safe.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-08-23 16:49:15 +02:00
Archit Taneja 438524c60f dt/bindings: qcom_nandc: Add DT bindings
Add DT bindings document for the Qualcomm NAND controller driver.

Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-03-10 10:52:22 -08:00