Commit graph

6 commits

Author SHA1 Message Date
Thierry Reding ddfb406b2f drm/tegra: dsi: Add Tegra210 support
The DSI host controller hasn't changed from Tegra132 to Tegra210, but
different characterization parameters may be required.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:45 +02:00
Thierry Reding 0fffdf6ca9 drm/tegra: dsi: Implement host transfers
Add support for sending MIPI DSI command packets from the host to a
peripheral. This is required for panels that need configuration before
they accept video data.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:12:36 +01:00
Thierry Reding e94236cde4 drm/tegra: dsi: Add ganged mode support
Implement ganged mode support for the Tegra DSI driver. The DSI host
controller to gang up with is specified via a phandle in the device tree
and the resolved DSI host controller used for the programming of the
ganged-mode registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:12:28 +01:00
Thierry Reding f7d6889b79 drm/tegra: dsi - Use internal pixel format
The pixel format enumeration values used by the Tegra DSI controller
don't match those defined by the DSI framework. Make sure to convert
them to the internal format before writing it to the register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-05 23:09:26 +02:00
Thierry Reding 9a2ac2dcdc drm/tegra: Relicense under GPL v2
The majority of the code in this driver is licensed under the GPL v2, so
relicense the rest under GPL v2 as well for consistency.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-04 09:12:51 +02:00
Thierry Reding dec727399a drm/tegra: Add DSI support
This commit adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features like ganged
mode won't work.

Due to the lack of other test hardware, some sections of the driver are
hardcoded to work with Dalmore.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-20 15:56:04 +01:00