At most of cases, the system allocated sg buffers for 4KB, but
the TD could contain 5 * 4KB non-contiguous buffers at most. In order
to avoid more chained TDs, we tried to put more sg buffers in one
TD instead of putting only one sg buffer.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
With commit d2e892c29d ("MLK-23595-1 usb: cdns3:
gadget: calculate TDL per TD"), the first trb->length assignment
is moved before the do-while loop, but only considering DEV_VER_V2
situation, in fact, we need to initialize trb->length for all situations.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
"fsl,imx8qm-usb" is not defined at driver, and "fsl,imx27-usb"
is older model. We need to use the closest model for it to get
the newer features, like runtime pm.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
The hsiomix power domain need to be runtime always-on to maintain USB's
wakeup ability. As this domain need to be boot on by default, no one will
call the power on callback during system boot up, the clock enable/disable
will mismatch, so remove the clocks from this domain. the necessary clocks
will be handled in TF-A.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Some power domain need to be runtime always on to keep
the peripherals's weekup ability, for such power domain,
add the 'GENPD_FLAG_RPM_ALWAYS_ON' flag.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
As eos event, when receive res change event from FW,
don't send it to framework until dst done_list is empty.
Avoid to framework ignore a few decoded frames.
Signed-off-by: Shijie Qin <shijie.qin@nxp.com>
Reviewed-by: ming_qian <ming.qian@nxp.com>
Update enet wakeup interrupt number since they are different
with imx8qxp.
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add aliases for ethernet node to support set mac
address by uboot ethnaddr env.
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Different HSIO usecase may be used by customers.
- add PCIEAx2PCIEBx1 usecase for example.
Only verified PCIA one lane refer to the iMX8QM MEK and Baseboard
hardware limitation.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Enable the second PCIe port PCIEB on i.MX8QM platforms.
- PCIEB has one more PER clock, since that the PCIEA CSR register
would be configuired when PCIEB is initialized.
- Use CLKREQ override on i.MX8QM/i.MX8QXP
- In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory
required by PCIEB. Otherwise PCIEB can't link up when exist from L2
mode when only PCIEB is used.
- Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
- Enable the PCIEB port on the i.MX8QM MEK and base board.
- In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory
required by PCIEB. Otherwise PCIEB can't link up when exist from
L2 mode when only PCIEB is used.
- PCIEB has one more PER clock, since that the PCIEA CSR register
would be configuired when PCIEB is initialized.
- Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
only cpu will access the v4l2 buffer of output stream,
so there is no need for allocate dma for it
use virtual memory can decreate the usage of dma,
and won't bring side effort
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Add the PCIe DMA IRQ name.
Enable the PCIe EP RC validation on iMX8MP EVK boards.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Move clocks prepare_enable and disable_unprepare calls
into runtime_resume and runtime_suspend respectively.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Move static XCVR IP configuration code into firmware load
method in order to avoid the need to have bus clock started
in "startup" callback.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Set watermarks values at half FIFO size, and max burst to 1/8
of FIFO size.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
"startup" callback is not called in a subsequent
"runtime_resume" sequence, so move IP init code
into "prepare" callback. Aside of this move
constraint check code from "prepare" to "startup"
since constraint checking is required once at stream
startup.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Refactor constraint handling in order to facilitate
unimplemented cases, such as for ARC and SPDIF.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Workaround that force mode_set to recovery hdmi2.0 and DP display
after cable plugin could work for weston 7.0,
But it failed work for weston 8.0 becuase atomic check will break.
Fixed it with force mode_set only when drm_atomic_state.allow_modeset is true.
and drm_atomic_check_only will success.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Because our relase image include m4 image by default, but dts for two
ov5640 don't include rpmsg, so user need to burn non-rpmsg flash.bin
if they want to test two ov5640 case. Test team and more and more guys
request to add rpmsg ov5640. The patch is used for the purpose.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Ov5640 will output some black frames at first when switch to other
resolution. So add about 100ms delay and software powerdown sensor
after finishing current video stream and before starting another
video stream to wait for sensor stable.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Need flush outer cache after zero CMA allocated memory on arm32 platform.
Change-Id: Ieaa7c62bf65e4490f904d68bed1fa16fb7c5d8fa
Signed-off-by: Richard Liu <xuegang.liu@nxp.com>
Reviewed-by: Bing Song <bing.song@nxp.com>
Suggest to use vmalloc for fifo entity.
Then use kfifo_init to init the fifo structure.
Then we do not have to require contiguous memory from buddy,
especially in a high pressure of memory resource.
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Change sai to master for bt-sco to resolve the long latence issue
for uplink
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Correct the legacy INTX numbers of the iMX8DXL PCIe.
Use the internal PLL as PCIe REF clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
support only basic function
eqos network
USB1 and USB2 basic work
Only total 512MB in DDR3 evk boards
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Don't need to add one more buffer, if the buffer
size is same as ASRC_MAX_BUFFER_SIZE.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
In reboot, system will try to access regisers through
the dai controls, but the clock is not bind with regmap,
then system hang.
So we enable regcache_cache_only in probe to fix this
issue.
Fixes: d55d453fdf ("MLK-23618-11: ASoC: fsl_spdif: Don't bind clock with regmap")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Fixed coverity reported issues. Needn't check if point isn't be NULL.
Signed-off-by: Bing Song <bing.song@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
fix the build warning introduced by following commit.
commit 41bfdd516e
Author: Kuldeep Singh <kuldeep.singh@nxp.com>
Date: Tue Jan 7 18:56:49 2020 +0530
LF-18-3 spi: fsl-qspi: Allocate AHB memory dynamically for imx platforms
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
ION CMA memory default is cacheable, need flush cache after memset(),
else cache and physical memory not sync may cause problem.
Issue case:
VPU Video playback or GPU render have dirty line issue.
Root cause:
ION CMA allocate cacheable buffer and do memset(), some data still in cache
not in physical memory, VPU or GPU write the buffer with physical address,
or user call ion_mmap() to map the buffer through pgprot_writecombine() as
no-cache and write the buffer, later some CPU cache access trigger cache
flush, previous memset() data go to physical memory as dirty data.
Change-Id: I82b4cb61bbe6cffc687d452f9f81c1e35914d2f1
Signed-off-by: Richard Liu <xuegang.liu@nxp.com>
Reviewed-by: Bing Song <bing.song@nxp.com>
Peter Chen