Update the simplefb nodes for hdmi / tv-encoder out to point to
tcon0_ch1 instead of tcon0_ch0 as tcon clock.
While at it fix the clocks lines being longer than 80 chars.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Enable the display and TCON clocks that are needed to drive the display
engine, tcon and TV encoders.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fix pll3x2 and pll7x2 not having a parent clock, specifically this
fixes the kernel turning of pll3 while simplefb is using it when
uboot has configured things to use pll3x2 as lcd ch clk parent.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we've a clock node describing pll3 we must add it to the
simplefb nodes clocks lists to avoid it getting turned off when
simplefb is used.
This fixes the screen going black when using simplefb.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Enable pll3 and pll7 clocks that are needed by display clocks.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Seems like dram_gate 5 was forgotten when DRAM gating driver was added.
Add it.
Cc: stable@vger.kernel.org
Fixes: 0b4bf5a520 (ARM: dts: sun7i: Add DRAM gates)
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the SPDIF transceiver controller block to the A20 dtsi.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the SPDIF clock to the A20 dtsi.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the SPDIF TX pin to the A20 dtsi.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The video engine has its own module clock, which also includes a
reset control for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 SoC includes the Allwinner audio codec, capable of both 24-bit
playback and capture. This commit adds a device node for it.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The audio codec functional clock is a child of PLL2 and is used to control
the audio rate, enable it in the DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The A20 uses the PLL2 as the audio PLL, which is the parent of all the
other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
This patch add support to the keypad clock on sun7i
Signed-off-by: Yassin Jaffer <yassinjaffer@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
sun7i-a20.dtsi contains a cpufreq operating point at 0.9 volts. The minimum
CPU voltage for the Allwinner A20 SoC, however, is 1.0 volts. Thus, raise
the voltage for the lowest operating point to 1.0 volts in order to stay
within the SoC specifications. It is an undervolted setting that isn't
stable across all SoCs and boards out there.
Cc: <stable@vger.kernel.org> # v4.0+
Fixes: d96b716191 ("ARM: dts: sun7i: Add cpu clock reference and operating points to dtsi")
Signed-off-by: Timo Sigurdsson <public_timo.s@silentcreek.de>
Acked-by: Iain Paton <ipaton0@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:
- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- Cleanups for Renesas shmobile platforms
- Lots of added devices on LPC18xx
- Lots of added devices and boards on UniPhier
There's also some dependent code added here, in particular some branches
that are primarily merged through the clock tree.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"Ladies and gentlemen, we proudly announce to you the latest branch of
ARM device tree contents for the mainline kernel. Come and see, come
and see!
No less than twentythree thousand lines of additions! Just imagine the
joy you will have of using your mainline kernel on newly supported
hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
UniPhier hardware!
For those of you feeling less adventurous, added hardware support on
platforms such as TI DM814x and Gumstix Overo platforms might be more
of your liking.
We've got something for everyone here!
Ahem. Cough. So, anyway...
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:
- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- cleanups for Renesas shmobile platforms
- lots of added devices on LPC18xx
- lots of added devices and boards on UniPhier
There's also some dependent code added here, in particular some
branches that are primarily merged through the clock tree"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
ARM: tegra: Add gpio-ranges property
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
ARM: tegra: Add Tegra124 PMU support
ARM: tegra: jetson-tk1: Add GK20A GPU DT node
ARM: tegra: venice2: Add GK20A GPU DT node
ARM: tegra: Add IOMMU node to GK20A
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Enable the DFLL on the Jetson TK1
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
ARM: dts: rockchip: correct regulator power states for suspend
ARM: dts: rockchip: correct regulator PM properties
ARM: dts: vexpress: Use assigned-clock-parents for sp810
pinctrl: tegra: Only set the gpio range if needed
arm: boot: dts: am4372: add ARM timers and SCU nodes
ARM: dts: AM4372: Add the am4372-rtc compatible string
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
...
The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The current DTs were setting the cell size to 2, but used the default xlate
function that was assuming an interrupt cell size of 1, leading to the
second part of the cell (the flags) being ignored, while we were having an
inconsistent binding between the interrupts and gpio (that could also be
used as interrupts).
That "binding" doesn't work either with newer SoCs that have multiple irq
banks.
Now that we fixed the pinctrl driver to handle this like it should always
have been handled, convert the DT users, and while we're at it, remove the
size-cells property of PIO that is completely useless.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.
This patch enable the Security System on the Allwinner A20 SoC Device-tree.
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add a node for the otg/drc usb controller to sun7i-a20.dtsi
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.
Add the SRAM controller, the SRAM that it drives and the section that can
be used by the various devices.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
This patch reverts commit ccb4ada2f1 ("ARM: dts: sun7i: Add A20 SRAM and
SRAM controller"), commit e6f51e4bd2 ("ARM: dts: sun5i: Add A13 and A10s
SRAM and SRAM controller") and commit 6d92b80f35 ("ARM: dts: sun4i: Add
A10 SRAM and SRAM controller").
The bindings have been changed in the SRAM driver, and we need to
change the DT accordingly.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some boards (e.g. the BananaPro) use alternative pins for uart4, add a pinmux
entry for these.
Signed-off-by: Michael Ring <mail@michael-ring.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The pinctrl groups for SPI until now were also adding the chip selects in
the SPI pinctrl group.
This was causing a few issues, since a board was forced to use a random
number of chipselects, even though it might use one of these chip selects
for another pin.
The number of chipselects defined was also not the same from one group to
another because of different needs at the time these groups have been
introduced, resulting in no clear view from the board DTS on what exactly
is being muxed, which even might change in the future.
Solve this by creating different pinctrl groups for the chipselects and the
standard SPI pins (CLK, MOSI and MISO) so that we fix both issues.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A few lines (probably copy pasted) have an indentation mixing tabs and
spaces that triggers a checkpatch warning.
Fix those, and while we're at it, fix the space-indented sections.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A few lines in our DTSIs are over the 80 characters limit, making
checkpatch complain about that.
If possible (and relevant), wrap these lines to 80 characters.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The FSF address triggers a warning on checkpatch, saying that the FSF
license is already present in the Linux source code, and that it has
already changed in the past.
Remove it from our DT, as suggested.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Currently none of the target boards nor the driver supports
IR TX. However this pin is used in a few instances as a GPIO.
Split the pin ctrl descriptions so that only the IR RX is
configured to be used.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The clock driver now supports a muxable ahb clock. Update the dtsi
with the proper compatible and add the new parent clocks.
This also adds the new pll6/4 output for pll6 on sun7i-a20. The
output is not used on sun4/5i.
Also use assigned-clocks to reparent ahb to pll6. We want ahb to
have a stable, non-changing clock rate. cpu/axi clock rate changes
as a result of newly added cpufreq support.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.
Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[hdegoede@redhat.com: Do not change soc node name, change compatible to
sun4i-a10-sram-controller to match the driver change]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Sometimes we need to specify non-probably information for sdio devices in the
devicetree, this is done through child nodes addressed by the reg property,
whereby the reg property refers to the sdio function number, see;
Documentation/devicetree/bindings/mmc/mmc.txt
This commit adds the necessary address- and size-cells properties to the mmc
controller nodes in the dtsi files, so that dts files needing such a child
node do not need to specify these themselves.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The touchscreen controller in the A13 and later has a different temperature
curve than the one in the original A10, change the compatible for the A13 and
later so that the kernel will use the correct curve.
Reported-by: Tong Zhang <lovewilliam@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Without proper regulator support for individual boards, it is dangerous
to have overclocked/overvoltaged OPPs in the list. Cpufreq will increase
the frequency without the accompanying voltage increase, resulting in
an unstable system.
Remove them for now. We can revisit them with the new version of OPP
bindings, which support boost settings and frequency ranges, among
other things.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices. Additionaly the framework core underwent a bit of surgery with
two major changes. The boundary between the clock core and clock
providers (e.g clock drivers) is now more well defined with dedicated
provider helper functions. struct clk no longer maps 1:1 with the
hardware clock but is a true per-user cookie which helps us tracker
users of hardware clocks and debug bad behavior. The second major change
is the addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the regulator
framework. Unfortunately these changes to the core created some
breakeage. We think we fixed it all up but for this reason there are
lots of last minute commits trying to undo the damage.
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Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes contain the usual driver additions,
enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
devices.
Additionally the framework core underwent a bit of surgery with two
major changes:
- The boundary between the clock core and clock providers (e.g clock
drivers) is now more well defined with dedicated provider helper
functions. struct clk no longer maps 1:1 with the hardware clock
but is a true per-user cookie which helps us tracker users of
hardware clocks and debug bad behavior.
- The addition of rate constraints for clocks. Rate ranges are now
supported which are analogous to the voltage ranges in the
regulator framework.
Unfortunately these changes to the core created some breakeage. We
think we fixed it all up but for this reason there are lots of last
minute commits trying to undo the damage"
* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
clk: Only recalculate the rate if needed
Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
clk: qoriq: Add support for the platform PLL
powerpc/corenet: Enable CLK_QORIQ
clk: Replace explicit clk assignment with __clk_hw_set_clk
clk: Add __clk_hw_set_clk helper function
clk: Don't dereference parent clock if is NULL
MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
clk: shmobile: div6: Avoid division by zero in .round_rate()
clk: mxs: Fix invalid 32-bit access to frac registers
clk: omap: compile legacy omap3 clocks conditionally
clkdev: Export clk_register_clkdev
clk: Add rate constraints to clocks
clk: remove clk-private.h
pci: xgene: do not use clk-private.h
arm: omap2+ remove dead clock code
clk: Make clk API return per-user struct clk instances
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
clk: tegra: Add support for the Tegra132 CAR IP block
...
DT changes continue to be the bulk of our merge window contents.
We continue to have a large set of changes across the board as new platforms
and drivers are added.
Some of the new platforms are:
- Alphascale ASM9260
- Marvell Armada 388
- CSR Atlas7
- TI Davinci DM816x
- Hisilicon HiP01
- ST STiH418
There have also been some sweeping changes, including relicensing of DTS
contents from GPL to GPLv2+/X11 so that the same files can be reused in
other non-GPL projects more easily. There's also been changes to the
DT Makefile to make it a little less conflict-ridden and churny down
the road.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"DT changes continue to be the bulk of our merge window contents.
We continue to have a large set of changes across the board as new
platforms and drivers are added.
Some of the new platforms are:
- Alphascale ASM9260
- Marvell Armada 388
- CSR Atlas7
- TI Davinci DM816x
- Hisilicon HiP01
- ST STiH418
There have also been some sweeping changes, including relicensing of
DTS contents from GPL to GPLv2+/X11 so that the same files can be
reused in other non-GPL projects more easily. There's also been
changes to the DT Makefile to make it a little less conflict-ridden
and churny down the road"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits)
ARM: dts: Add PPMU node for exynos4412-trats2
ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato
ARM: dts: Add PPMU dt node for exynos4 and exynos4210
ARM: dts: Add PPMU dt node for exynos3250
ARM: dts: add mipi dsi device node for exynos4415
ARM: dts: add fimd device node for exynos4415
ARM: dts: Add syscon phandle to the video-phy node for Exynos4
ARM: dts: Add sound nodes for exynos4412-trats2
ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2
ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi
ARM: dts: Add max77693 charger node for exynos4412-trats2
ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2
ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2
ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2
ARM: dts: am57xx-beagle-x15: Fix USB2 mode
ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB
ARM: dts: dra72-evm: Add extcon nodes for USB
ARM: dts: dra7-evm: Add extcon nodes for USB
ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards
ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb
...
Commit f77d55a3b5 ("serial: 8250_dw: get index of serial line from DT
aliases") made the serial driver now use the serial aliases to get the tty
number, pointing out that our aliases have been wrong all along.
Remove them from the DTSI and add custom ones in the relevant boards.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch add missing mdio label for sun[457]i.
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The core temperature sensor now supports thermal zones. Add a thermal
zone mapping for the cpus with passive cooling (cpufreq throttling).
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add simplefb nodes for "[de_fe0-]de_be0-lcd0" and "[de_fe0-]de_be0-lcd0-tve0"
display pipelines for when u-boot has set up a pipeline to drive a LCD panel /
VGA output rather then the HDMI output.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The cpu core is clocked from the "cpu" clock. Add a reference to it
in the first cpu node. Also add "cpu0" label to the node.
The operating points were taken from the A20 FEX files in the
sunxi-boards repository. Not all boards have the same settings. The
settings in this patch are the most generic ones.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that the resistive touchpanel driver supports thermal sensors,
add the "#thermal-sensor-cells" property as required by the thermal
framework.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The GIC requires some extra opaque arguments to set the IRQ type and flags.
Convert the DTs to using the common defines.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The pinctrl nodes require some extra opaque arguments for the pull up and drive
strength values.
Introduce a new header file and convert the device trees to replace these
opaque numbers by defines.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The DMA engine for the A10/A20 and derivatives require an opaque extra
argument.
Add a dt-bindings header, and convert the device trees to it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Aleksei Mamlin