Enable both PCIe ports, one of which is connected to an onboard ethernet
chip, whereas the other goes to a miniPCIe slot.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, fixed PCIe supply property names in DT]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the PCIe controller device tree node and hook up the PCIe PHY from
the XUSB pad controller.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This is a Q8 format 7 inch tablet with an Allwinner A13 SoC.
It has 512MB DRAM, 4GB NAND flash, an accelerometer, camera,
RTL8188-based WiFi, and micro SD slot for external storage.
It is likely made by a subsidiary of Hanns.G (Hannstar).
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Most if not all boards we've seen have a fixed 5V regulator, which is
the main power supply and/or fixed output of the PMIC.
Add this one to the common regulators DTSI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Recent bootloader versions from Marvell that have DT support and
various other new features remap the internal registers at
0xf1000000. We have already done this change for most of the
development boards from Marvell, and this commit does this change for
the Marvell Armada 370 RD board.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1410961539-10388-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit adds a new platform-data boolean property that enables use
of a flash-based bad block table. This can also be enabled by setting
the 'nand-on-flash-bbt' devicetree property.
If the flash BBT is not enabled, the driver falls back to use OOB
bad block markers only, as before. If the flash BBT is enabled the
kernel will keep track of bad blocks using a BBT, in addition to
the OOB markers.
As explained by Brian Norris the reasons for using a BBT are:
""
The primary reason would be that NAND datasheets specify it these days.
A better argument is that nobody guarantees that you can write a
bad block marker to a worn out block; you may just get program failures.
This has been acknowledged by several developers over the last several
years.
Additionally, you get a boot-time performance improvement if you only
have to read a few pages, instead of a page or two from every block on
the flash.
""
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The corresponding bug in pm-sh7372.c was fixed in commit
70fe7b2467 ("ARM: shmobile: Do not access sh7372 A4S domain
internals directly").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
We are getting "PRM: I/O chain clock line assertion timed out" errors
on early omaps for device tree based booting. This is because we are
unconditionally calling reconfigure_io_chain while legacy booting
has omap3_has_io_chain_ctrl() checks in place in omap_hwmod.c.
For device tree based booting, we are calling reconfigure_io_chain
unconditionally from pinctrl framework. So we need to add a check for
omap3_has_io_chain_ctrl() to avoid the errors for trying to access
a register that does not exist.
For es3.0, the documentation in "4.11.2 Device Off-Mode Configuration"
just mentions PM_WKEN_WKUP[8] bit. For es3.1, there's a new chapter in
documentation for "4.11.2.2 I/O Wake-Up Mechanism" that describes the
PM_WKEN_WKUP[16] ST_IO_CHAIN bit. So PM_WKEN_WKUP[16] bit did not get
added until in es3.1 probaly to fix issues with flakey wake-up events.
We are doing proper checks for ST_IO_CHAIN already in id.c and with
omap3_has_io_chain_ctrl(). For more information, see also commit
b02b917211 ("ARM: OMAP3: PM: fix I/O wakeup and I/O chain clock
control detection").
Let's fix the issue by selecting the right function during init for
reconfigure_io_chain depending on the omap revision. For es3.0 and
earlier we need to just toggle EN_IO. By doing this, we can move the
check for omap3_has_io_chain_ctrl() from omap_hwmod.c to the init code
in prm_3xxx.c. And then we can unconditionally call reconfigure_io_chain.
Thanks to Paul Walmsley and Nishanth Menon for help with debugging the
issue.
Fixes: 30a69ef785 ("ARM: OMAP: Move DT wake-up event handling over to use pinctrl-single-omap")
Cc: Kevin Hilman <khilman@kernel.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Just move the code over as it has no dependencies
on arch/arm/ anymore.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP INTC irqchip driver will be moved under
drivers/irqchip/ soon but we still have a dependency
with mach-omap2 when it comes to idle functions.
In order to make it easy to share those function
prototypes with OMAP PM code, we introduce this new
header.
To avoid modifying several board-files and some of
the PM-related code, we just include the new header
from common.h which was already included by all
users of IRQ-related PM code.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
By moving i2c devices to DT we can clean up
i2c_board_info and fix a problem with moving
INTC to irq domain where IRQs can be renumbered
on each boot.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix a copy'n'paste error making the rk3188 emmc pinctrl nodes reference
the pcfg_pull_default setting that is not available on rk3188.
Reported-by: Naoki FUKAUMI <naobsd@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The host and otg regulator pinctrl settings got swapped, making the host
reference the otg pinctrl and the other way round. The actual pins are
correct (gpio0-3 for host and gpio2-31 for otg).
Reported-by: Naoki FUKAUMI <naobsd@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
As Acme Systems Fox G20 is available in Device Tree flavor and that we plan to
remove all the board files soon, we can remove this one without problem.
If you use this board, please use a DT-enabled at91sam9g20 kernel with
at91-foxg20.dts.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Sergio Tanzilli <tanzilli@acmesystems.it>
This defconfig already enables DEBUG_LL and by default DEBUG_LL_UART_NONE
will be selected (but due to some back compability magic I'd like to
remove is not actually honoured). DEBUG_LL_UART_PL01X is a much saner
default.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This defconfig already enables DEBUG_LL and by default DEBUG_LL_UART_NONE
will be selected (but due to some back compability magic I'd like to
remove is not actually honoured). DEBUG_LL_UART_PL01X is a much saner
default.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rob Clark reports a sleeping while atomic bug when using perf.
BUG: sleeping function called from invalid context at ../kernel/locking/mutex.c:583
in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/0
------------[ cut here ]------------
WARNING: CPU: 2 PID: 4828 at ../kernel/locking/mutex.c:479 mutex_lock_nested+0x3a0/0x3e8()
DEBUG_LOCKS_WARN_ON(in_interrupt())
Modules linked in:
CPU: 2 PID: 4828 Comm: Xorg.bin Tainted: G W 3.17.0-rc3-00234-gd535c45-dirty #819
[<c0216690>] (unwind_backtrace) from [<c0212174>] (show_stack+0x10/0x14)
[<c0212174>] (show_stack) from [<c0867cc0>] (dump_stack+0x98/0xb8)
[<c0867cc0>] (dump_stack) from [<c02492a4>] (warn_slowpath_common+0x70/0x8c)
[<c02492a4>] (warn_slowpath_common) from [<c02492f0>] (warn_slowpath_fmt+0x30/0x40)
[<c02492f0>] (warn_slowpath_fmt) from [<c086a3f8>] (mutex_lock_nested+0x3a0/0x3e8)
[<c086a3f8>] (mutex_lock_nested) from [<c0294d08>] (irq_find_host+0x20/0x9c)
[<c0294d08>] (irq_find_host) from [<c0769d50>] (of_irq_get+0x28/0x48)
[<c0769d50>] (of_irq_get) from [<c057d104>] (platform_get_irq+0x1c/0x8c)
[<c057d104>] (platform_get_irq) from [<c021a06c>] (cpu_pmu_enable_percpu_irq+0x14/0x38)
[<c021a06c>] (cpu_pmu_enable_percpu_irq) from [<c02b1634>] (flush_smp_call_function_queue+0x88/0x178)
[<c02b1634>] (flush_smp_call_function_queue) from [<c0214dc0>] (handle_IPI+0x88/0x160)
[<c0214dc0>] (handle_IPI) from [<c0208930>] (gic_handle_irq+0x64/0x68)
[<c0208930>] (gic_handle_irq) from [<c0212d04>] (__irq_svc+0x44/0x5c)
Exception stack(0xe63ddea0 to 0xe63ddee8)
dea0: 00000001 00000001 00000000 c2f3b200 c16db380 c032d4a0 e63ddf40 60010013
dec0: 00000000 001fbfd4 00000100 00000000 00000001 e63ddee8 c0284770 c02a2e30
dee0: 20010013 ffffffff
[<c0212d04>] (__irq_svc) from [<c02a2e30>] (ktime_get_ts64+0x1c8/0x200)
[<c02a2e30>] (ktime_get_ts64) from [<c032d4a0>] (poll_select_set_timeout+0x60/0xa8)
[<c032d4a0>] (poll_select_set_timeout) from [<c032df64>] (SyS_select+0xa8/0x118)
[<c032df64>] (SyS_select) from [<c020e8e0>] (ret_fast_syscall+0x0/0x48)
---[ end trace 0bb583b46342da6f ]---
INFO: lockdep is turned off.
We don't really need to get the platform irq again when we're
enabling or disabling the per-cpu irq. Furthermore, we don't
really need to set and clear bits in the active_irqs bitmask
because that's only used in the non-percpu irq case to figure out
when the last CPU PMU has been disabled. Just pass the irq
directly to the enable/disable functions to clean all this up.
This should be slightly more efficient and also fix the
scheduling while atomic bug.
Fixes: bbd6455937 "ARM: perf: support percpu irqs for the CPU PMU"
Reported-by: Rob Clark <robdclark@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The TPIDRURO and TPIDRURW registers need to be flushed during exec;
otherwise TLS information is potentially leaked. TPIDRURO in
particular needs careful treatment. Since flush_thread basically
needs the same code used to set the TLS in arm_syscall, pull that into
a common set_tls helper in tls.h and use it in both places.
Similarly, TEEHBR needs to be cleared during exec as well. Clearing
its save slot in thread_info isn't right as there is no guarantee
that a thread switch will occur before the new program runs. Just
setting the register directly is sufficient.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Previous commits that dealt with get_user for 64bit type missed to
export proper functions, so if get_user macro with particular target/value
types are used by kernel module modpost would produce 'undefined!' error.
Solution is to export all required functions.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
AUX setting has no effect that's why remove it.
Warning log:
L2C: platform provided aux values match the hardware, so
have no effect. Please remove them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Match the naming pattern of all other SMP ops and rename
zynq_platform_cpu_die --> zynq_cpu_die.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The hotplug code contains only a single function, which is an SMP
function. Move that to platsmp.c where all other SMP runctions reside.
That allows removing hotplug.c and declaring the cpu_die function
static.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Avoid races and add synchronisation between the arch specific
kill and die routines.
The same synchronisation issue was fixed on IMX platform
by this commit:
"ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill"
(sha1: 2f3edfd7e2)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As there is no Power management unit on this board, it is not possible to power
down a core, just WFI is allowed. There is no point to invalidate the cache and
exit coherency.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add the DDR controller to the Zynq devicetree.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is an ISL9305 regulator on the Parallella board, add it to the DT
along with descriptions of all the supplies.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Other R-Car Gen2 SoCs such as r8a7790 and r8a7791 reserve
the top 256 MiB of memory for use with CMA. Adjust the
board-less r8a7794 code to do the same.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Original gpt per clk parent is from ipg_per clk which
may be scaled when system enter low bus mode, as ipg
clk will be lower in low bus mode, to keep system clk
NOT drift, select gpt per clk parent from OSC which
is at fixed freq always.
On i.mx6qdl, add a osc_per clk source for i.mx6q
TO > 1.0 and all i.MX6dl SoC.
On i.mx6sx, just make gpt per clk from OSC.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The GW52xx baseboard supports CANbus so we enable it, configure its pinmux
and CAN_STBY gpio.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Follow the conventions for pinctrl:
- grouping pinctrl in logical alphabatized groups
- remove any pinctrl not being used by a driver or needed by user
- move iomuxc to bottom of file for readability
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Follow the convention of configuring padconf for all pins and not leaving
any 0x80000000 to leave them un-configured.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Use the gpio contants defined in bindings for active high/low
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Remove aliases that are either not used by bootloader or are provided via
included dtsi files.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The general device-tree rule is to not include nodes that do not have a driver
or bindings in a dts/dtsi. Remove the place-holder nodes from the Gateworks
Ventana boards until a time that a driver with proper bindings exists.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This alias is used by U-Boot to enable/disable the regulator depending
on baseboard type.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The spi-mxs driver does not allow full duplex SPI transfers. The
spi-gpio driver may be used as an alternative if this is required.
Make the choice between those drivers easier for the end user by
providing settings for both drivers.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The labels on the spidev nodes are not used and not required, so
remove them. The TX28 supports 3 chipselects on the SPI
interface. Make all those chipselects available to the user.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Baud clock is used for bit clock generation in master mode. Ipg clock
is peripheral clock and peripheral access clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Baud clock is used for bit clock generation in master mode. Ipg clock
is peripheral clock and peripheral access clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Passing '0x80000000' to the pin configuration means that kernel will skip the
IOMUXC_SW_PAD_CTL configuration and will use whathever values come from the
bootloader.
Instead of relying on the bootloader setup, let's configure it in the kernel to
have predictable settings.
'0x1b0b0' is the default POR value for all these pins and has also been verified
that the pins are using this value by manually inspecting the IOMUXC_SW_PAD_CTL
registers, so no functional change has been made.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the wa
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@02220000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The lcdif node has a property named "display" and also a child node
called "display", which causes the following warning:
device-tree: Duplicate name in lcdif@80030000, renamed to "display#1"
Rename the child node name in order to avoid the warning.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
imx6sx has the same LCDIF controller IP as in mx28, so add the proper
compatible strings.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fixes "imx6q-pcie 1ffc000.pcie: missing *config* reg space"
error exposed by new versions of the designware pcie driver.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds support for the i.MX1 APF9328 from Armadeus.
This change is intended to further remove non-DT support for this board.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add the IOMUX setting for the IR input, rather than relying on the
boot loader.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
HummingBoard after rev 2.0 and the production one starting rev 3.0 uses
gpio 3,5 (EIM_DA5 pad) as the gpio infra red receiver input.
Since the original Carrier1 board is obsolete and we are retiring it,
update the DT file for this. This will mean IR reception will not
work on Carrier1 with this DT file.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Initial patch from Rabeeh, but with the electrical properties added.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The i.MX53 has a Cortex-A8 Performance Monitor Unit.
Add it to the dtsi.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds the battery backed real time clock connected to I2C1
to the device tree.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds simple-card support to the i.MX SoCs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds support for the Freescale (Motorola) i.MX1 ADS board.
This change is intended to further remove non-DT support for this board.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add USB support for Freescale Vybrid tower. The USB hosts over-current
protection signal is not connected to the PHY's over- current
protection, hence we need to disable it.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add USB support for Colibri VF61 modules. The Colibri standard pinout
defines a pin for USB over-current. However, due to lack of pinmux
options, the USB hosts over-current protection signal of the Colibri
standard could not be connected to the PHY's over-current protection.
Hence we need to disable the over-current functionality of the USB
controller.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add device tree node for usbmisc which controls the non-core USB
registers. This is required to use the property to disable the over-
current detection.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This adds USB PHY and USB controller nodes. Vybrid SoCs have two
independent USB cores which each supports DR (dual role). However,
real OTG is not supported since the OTG ID pin is not available.
The PHYs are located within the anadig register range, hence we need
to change the length of the anadig registers.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
[ukl: rebase from ancient kernel version]
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The preloaded script addresses on imx25 and imx35 are different, so
imx25 is not compatible with imx35-sdma unless a custom firmware is
loaded.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds basic devicetree template for i.MX1 based SoCs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Everything in the PCI specification assumes devices to be
enumerable on startup. This is only possible if they have
power available.
A future improvement may allow this regulator to be switched
off for D3hot and D3cold power states, but there is a lot
of work to do the pcie host controller side for this to work.
To keep things simple always enable the regulator for now.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The Colibri VF61 is a module which needs a carrier board to actually
run. Different carrier board have different hardware support, hence
we should reflect this in the device tree files. This patch adds the
Colibri Evaluation Board, which supports almost all peripherals
defined in the Colibri standard.
Also align the compatible naming, file splitting and file naming with
the scheme which was choosen for the Tegra based modules.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by
default.
The fsl sai driver is used by the vf610-twr board, so let's enable it by
default.
simple-audio-card driver is used by the vf610-twr board, so let's enable it by
default.
Generated this patch by doing:
- make imx_v6_v7_defconfig
- make menuconfig and manually select options
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by
default.
Generated this patch by doing:
- make imx_v4_v5_defconfig
- make menuconfig and manually select CONFIG_IMX_WEIM
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v4_v5_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.
There are some difference on this implementation of
gpt per clock source, see below for details:
i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock
of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC
for gpt per clk, and we must enable GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
There is a copy&paste error on register offset of pll7_usb_host gate
clock introduced by i.MX6 PLL bypass support patches. The error breaks
the ENET function, because it overwrites the pll6_enet gate bit.
Correct the offset for all i.MX6 clock drivers.
Thanks to Fugang Duan <B38611@freescale.com> for spotting the error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sx.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The imx6q clock driver currently hard-codes all PLL clocks to source
from OSC24M without BYPASS support. The patch adds the missing lvds_in
clock which is mutually exclusive with lvds_gate, and implements BYPASS
and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary
Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits
are implemented as mux clocks, and ENABLE bit of PLL clocks is
implemented as a gate clock after BYPASS mux.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously.
This patches adds an exclusive gate clock type specifically for such
case. The clock driver will need to call imx_clk_gate_exclusive() to
register a gate clock with parameter exclusive_mask indicating the mask
of gate bits which are mutually exclusive to this gate clock.
Right now, it only handles the exclusive gate clocks which are defined
in a single hardware register, which is the case we're running into
today. But it can be extended to handle exclusive gate clocks defined
in different registers later if needed.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share
the same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename
'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'.
Make the clock for ESAI more clear and align them with imx6sx.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Currently csi_lcdif_sels[] is a shared array for the providing the possible
clock parents for csi and lcdif blocks.
This is not correct, as csi and lcdif do not share the same clock parents.
Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in
order to describe the parents correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit adds PLL7 which is required for USBPHY1. It also adds
the USB PHY and USB Controller clocks and the gates to enable them.
Acked-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add cpufreq support for i.MX6SX, using common
i.MX6Q cpufreq driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
At the end of the boot process, the clock framework might disable
required main PLL's. So far, this was no issue since drivers
requested clocks, which are descended of the main PLL's (e.g.
pll1_pfd1, which provides the system clock).
To archive the full 500MHz system clock, DDR clock need to be a
descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The
bootloader sets up the clocks accordingly before making use of
DDR at all. However, in Linux, there is no driver using PLL2,
which lead to PLL2 being disabled by the clock framework.
With this patch, we make sure that the main system clock and the
DDR clock are initially enabled and are kept enabled.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch adds basic devicetree support for i.MX1 based SoCs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3
and TO1.4 are never revealed.
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
The interrupt controller used the generic compatible property only.
Add the SoC-specific one, to make it future proof.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This change makes it so that instead of passing and storing a mii_bus we
instead pass and store a host_dev. From there we can test to determine the
exact type of device, and can verify it is the correct device for our switch.
So for example it would be possible to pass a device pointer from a pci_dev
and instead of checking for a PHY ID we could check for a vendor and/or device
ID.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Now that we don't depend on anyting in the mach-at91 directory, we can just
move the driver to where it belongs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Conflicts:
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
This allows to remove the dependency of the timer driver on mach/hardware.h and
having an hardcoded interrupt number in the driver itself.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
In preparation for DT support where panel timings will be described by a
DRM-agnostic video mode, replace the struct drm_mode_modeinfo instance
in the panel platform data with a struct videomode.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The bootloader on the Netgear ReadyNAS RN102 uses Hardware BCH ECC
(strength = 4), while the pxa3xx NAND driver by default uses
Hamming ECC (strength = 1).
This patch changes the ECC mode on these machines to match that
of the bootloader and of the stock firmware. That way, it is
now possible to update the kernel from userland (e.g. using
standard tools from mtd-utils package); u-boot will happily
load and boot it.
Fixes: 92beaccd8b ("ARM: mvebu: Enable NAND controller in ReadyNAS 102 .dts file")
Cc: <stable@vger.kernel.org> #v3.14+
Signed-off-by: Ben Peddell <klightspeed@killerwolves.net>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/1410339341-3372-1-git-send-email-klightspeed@killerwolves.net
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
drivers/usb/phy/phy-samsung-usb2 driver got replaced by
drivers/phy/phy-samsung-usb2 one. Remove the leftover
USB2 PHY node (EHCI/OHCI USB nodes are using the new one
already) from Exynos5250 dtsi file.
Cc: Mark Brown <broonie@linaro.org>
Cc: Kamil Debski <k.debski@samsung.com>
Cc: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add DT nodes for panel-simple "auo,b133htn01" panel.
Add backlight enable pin and backlight power supply for pwm-backlight.
Also, add panel phandle needed by dp to enable display on peach_pi.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Since one of the platforms (Armada 370 RD) is now using the gpio-fan
driver, it makes sense to enable it in mvebu_v7_defconfig.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1410429419-29820-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
For some reason, while all other features are configured built-in, the
LED class support was configured as a module in
mvebu_v7_defconfig. This commit makes it consistent with the other
options, by making this feature built-in.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1410429419-29820-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370 RD has a GPIO controlled LED connected on MPP32, so
this commit adds the relevant hardware description to Armada 370 RD
Device Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1410429419-29820-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370 RD platform has a GPIO-controlled fan on MPP8, so this
commit adds the relevant hardware description to Armada 370 RD Device
Tree.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1410429419-29820-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
During the conversion of boards to use DT to instantiate Distributed
Switch Architecture, nobody volunteered to test. As to be expected,
the conversion was flawed. Testers and access to hardware has now
become available, and this patch hopefully fixes the problems.
dsa,mii-bus must be a phandle to the top level mdio node, not the port
specific subnode of the mdio device.
dsa,ethernet must be a phandle to the port subnode within the ethernet
DT node, not the ethernet node.
Don't pinctrl hog the card detect gpio for mvsdio.
Rename the .dts files to make it clearer which file is for the Z0
stepping and which for the A0 or later stepping.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Cc: seugene@marvell.com
Tested-by: Eugene Sanivsky <seugene@marvell.com>
Fixes: e2eaa339af: ("ARM: Kirkwood: convert rd88f6281-setup.c to DT.")
Fixes: e7c8f3808b: ("ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT")
Cc: <stable@vger.kernel.org> #v3.15+
Link: https://lkml.kernel.org/r/1409592941-22244-1-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Commit 356649ab6d ("ARM: dts: rockchip: unuse the slot-node and deprecate
the supports-highspeed for dw-mmc") removed the slots but not the #xx-cells
properties describing the subnodes. Do this now.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the controller node, pinctrl settings for the customizable pins
and sort the controllers like on rk3288 as emmc, sdmmc, sdio for
handling convenience.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This enables both the otg and host port and adds the vbus regulators
on the Radxa Rock board. As we don't have phy support yet, the vbus
regulators are added in always-on mode.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This is a remnant from the first i2c driver iteration that seems to have
been forgotten and thus made its way into the dtsi. Remove it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The restart-handler series from Guenter Roeck got accepted recently and
implements among other things also the restart handler in the samsung
watchdog driver and where applicable in the clock drivers. So there is
no need for having the restart callbacks in s3c24xx boards anymore.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Commit b3205dea8f ("ARM: EXYNOS: Map SYSRAM through generic DT
bindings") introduced local variable boot_reg where boot address from
cpu_boot_reg() call is stored. Re-use it instead calling cpu_boot_reg()
again.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add DT nodes for ps8622 bridge chip and panel.
Add backlight power supply for pwm-backlight.
Also add bridge phandle needed by dp to enable display on peach_pit.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add DT nodes for ptn3460 bridge chip and panel.
Add backlight enable pin and backlight power supply for pwm-backlight.
Also add bridge phandle needed by dp to enable display on snow.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
ARM irq work IPI support depends on SMP support. That information is
partly known at early boottime. Lets implement
arch_irq_work_has_interrupt() accordingly.
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
The nohz full code needs irq work to trigger its own interrupt so that
the subsystem can work even when the tick is stopped.
Lets introduce arch_irq_work_has_interrupt() that archs can override to
tell about their support for this ability.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
The Peach Pi board has an Atmel maXTouch trackpad device.
Add the needed Device Tree nodes to support it.
This Device Tree change is based on the Chrome OS 3.8 tree
but adapted to use the mainline Atmel maXTouch DT binding.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Peach Pit board has an Atmel maXTouch trackpad device.
Add the needed Device Tree nodes to support it.
This Device Tree change is based on the Chrome OS 3.8 tree
but adapted to use the mainline Atmel maXTouch DT binding.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The downstream ChromeOS 3.8 kernel sets the clock frequency
for the I2C bus 7 at 400kHz. Do the same change in mainline.
Suggested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Exynos5420 based Peach Pit and the Exynos5800 based Peach Pi
machines have an i2c ISL29018 light sensor. This patch adds the
device nodes needed to support this device.
These DTS snippets were taken from the downstream Chrome OS 3.8
kernel Device Tree for Peach Pit and Pi boards.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch creates a thermistor fragment carrying the NTC
Thermistor nodes as children of the IIO based ADC.
This fragment is included in exynos5420-peach-pit.dts and
exynos5800-peach-pi.dts.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adding regulators for hdmi for peach-pit board.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adding regulators for HDMI for Peach-pi board.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5420 based Peach Pit and Exynos5800 based Peach Pi boards
uses a Maxim 77802 power management IC to drive regulators and
its Real Time Clock. This patch adds support for this chip.
These are the device nodes and pinctrl configuration that
are present on the Peach pit DeviceTree source file in the
the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arm64.
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Merge tag 'stable/for-linus-3.17-b-rc4-arm-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip
Pull Xen ARM bugfix from Stefano Stabellini:
"The patches fix the "xen_add_mach_to_phys_entry: cannot add" bug that
has been affecting xen on arm and arm64 guests since 3.16. They
require a few hypervisor side changes that just went in xen-unstable.
A couple of days ago David sent out a pull request with a few other
Xen fixes (it is already in master). Sorry we didn't synchronized
better among us"
* tag 'stable/for-linus-3.17-b-rc4-arm-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip:
xen/arm: remove mach_to_phys rbtree
xen/arm: reimplement xen_dma_unmap_page & friends
xen/arm: introduce XENFEAT_grant_map_identity
The Brahma-B15's ISAR0 correcty advertises UDIV/SDIV support in both ARM
and Thumb2 modes (CPUID_EXT_ISAR0=02101110), so we don't need to
manually apply this hwcap.
The code in question actually predates the following commit, which made
our hwcaps unnecessary:
commit 8164f7af88
Author: Stephen Boyd <sboyd@codeaurora.org>
Date: Mon Mar 18 19:44:15 2013 +0100
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This adds the Atmel Micro ASIC platform device and selects it
by default for h3100 and h3600.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
e38361d 'ARM: 8091/2: add get_user() support for 8 byte types' commit
broke V7 BE get_user call when target var size is 64 bit, but '*ptr' size
is 32 bit or smaller. e38361d changed type of __r2 from 'register
unsigned long' to 'register typeof(x) __r2 asm("r2")' i.e before the change
even when target variable size was 64 bit, __r2 was still 32 bit.
But after e38361d commit, for target var of 64 bit size, __r2 became 64
bit and now it should occupy 2 registers r2, and r3. The issue in BE case
that r3 register is least significant word of __r2 and r2 register is most
significant word of __r2. But __get_user_4 still copies result into r2 (most
significant word of __r2). Subsequent code copies from __r2 into x, but
for situation described it will pick up only garbage from r3 register.
Special __get_user_64t_(124) functions are introduced. They are similar to
corresponding __get_user_(124) function but result stored in r3 register
(lsw in case of 64 bit __r2 in BE image). Those function are used by
get_user macro in case of BE and target var size is 64bit.
Also changed __get_user_lo8 name into __get_user_32t_8 to get consistent
naming accross all cases.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Suggested-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
According to the ARM ARMv7, explicit barriers are necessary when using
synchronisation primitives such as SWP{B}. The use of these
instructions does not automatically imply a barrier and any ordering
requirements by the software must be explicitly expressed with the use
of suitable barriers.
Based on this, remove the barriers from SWP{B} emulation.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Minor fixes for amba-clcd and video DT bindings.
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Merge tag 'fbdev-fixes-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux
Pull fbdev fixes from Tomi Valkeinen:
"Minor fixes for amba-clcd and video DT bindings"
* tag 'fbdev-fixes-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux:
video: ARM CLCD: Fix color model capabilities for DT platforms
video: fix composite video connector compatible string
now that we don't need to support legacy board-files,
we can completely switch over to a linear irq domain
and make use of irq_alloc_domain_generic_chips() to
allocate all generic irq chips for us.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we don't need the ifdef if we have omap_nr_pending
telling us how many pending registers we have
on current platform. This solves a possible
problem where we could try to handle bogus
interrupts on OMAP2 and OMAP3 if using single
zImage kernel, because we would end up reading
the following pending FIQ register.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
that variable will tell us how many INTC_PENDING_IRQn
registers we have. It'll be used on a following patch
to cleanup omap_intc_handle_irq() a bit.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we can set our global omap_nr_irqs early on
and drop the extra argument to omap_init_irq().
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
that was just a no-op wrapper around omap_intc_handle_irq
anyway.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
now that we're calling set_handle_irq() from
init_irq(), we can safely drop all callers to
omap3_intc_handle_irq() and its definition.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
the idea is that board-files won't need to set
.handle_irq on their machine_descs, which lets
us drop a little more pointless code.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We want .init_irq to call set_irq_handle() for
legacy platforms. Note that this code will also
be dropped once omap2/3 devices are completely
moved to DT.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we are now infering number of IRQ lines based
on correct compatible flag, which renders this
binding completely useless.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we don't need that anymore since specific
devices are passing correct compatible flags.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
that way, our intc driver can figure out how
many IRQ lines INTC has.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
so far, only am33xx has 128 lines, all other devices
have only 96.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
with this, we can use a compatible flag to figure
out how many irq lines are wired up, no need for
our TI-specific ti,intc-size binding.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
now we can safely drop those fields from our machine_desc.
While at that, also drop the now unused omap_intc_of_init()
definition.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
IRQCHIP_DECLARE macro is used to declare the same
of_device_id structure for irqchips, it's just
a helper. No functional changes.
Note that we're temporarily including irqchip.h
with its full path, until we move this driver
to drivers/irqchip/.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
this will let us drop .handle_irq and .init_irq fields
from our generic machine_descs.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
nobody uses that function outside of this file,
so we don't need to expose it.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
remove ifdef around omap3 INTC support. This
will make it easier to reuse code for PM.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
omap_intc_handle_irq now had an unnecessary
base_addr argument. Let's remove it and fix
all callers.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
an almost blind conversion from readl_relaxed
to our newly introduced intc_readl().
While at that, also remove some hardcoded
register addresses.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
this will cache number of irqs. Also in preparation
for removal of irq_banks array.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We have a single bank in that array, this patch
is in preparation to remove that array. It just
shifts everything to a new set of functions
for register IO while also removing old ones.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This is in preparation for removing the pointless
irq_banks array.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
of_device_ids (i.e. compatible strings and the respective data) are not
supposed to change at runtime. All functions working with of_device_ids
provided by <linux/of.h> work with const of_device_ids. So mark the
non-const function parameters and structs for OMAP2+ as const, too.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The definition
static const char *omap3_boards_compat[] __initconst = {
defines a changable array of constant strings. That is you must not do:
*omap3_boards_compat[0] = 'f';
but
omap3_boards_compat[0] = "another string";
is fine. So the annotation __initconst is wrong and yields a compiler
error when other really const variables are added with __initconst.
As the struct machine_desc member dt_compat is declared as
const char *const *dt_compat;
making the arrays const is the better alternative over changing all
annotations to __initdata.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that the restart code has been merged in the watchdog driver, we don't need
the restart code in the mach-sunxi directory anymore.
Remove it entirely.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The sub-mailbox devices are added to the Mailbox DT nodes on
OMAP2420, OMAP2430, OMAP3, AM33xx, AM43xx, OMAP4 and OMAP5
family of SoCs. This data represents the same mailboxes that
used to be represented in hwmod attribute data previously.
The node name is chosen based on the .name field of
omap_mbox_dev_info structure used in the hwmod data.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove the rbtree used to keep track of machine to physical mappings:
the frontend can grant the same page multiple times, leading to errors
inserting or removing entries from the mach_to_phys tree.
Linux only needed to know the physical address corresponding to a given
machine address in swiotlb-xen. Now that swiotlb-xen can call the
xen_dma_* functions passing the machine address directly, we can remove
it.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Tested-by: Denis Schneider <v1ne2go@gmail.com>
xen_dma_unmap_page, xen_dma_sync_single_for_cpu and
xen_dma_sync_single_for_device are currently implemented by calling into
the corresponding generic ARM implementation of these functions. In
order to do this, firstly the dma_addr_t handle, that on Xen is a
machine address, needs to be translated into a physical address. The
operation is expensive and inaccurate, given that a single machine
address can correspond to multiple physical addresses in one domain,
because the same page can be granted multiple times by the frontend.
To avoid this problem, we introduce a Xen specific implementation of
xen_dma_unmap_page, xen_dma_sync_single_for_cpu and
xen_dma_sync_single_for_device, that can operate on machine addresses
directly.
The new implementation relies on the fact that the hypervisor creates a
second p2m mapping of any grant pages at physical address == machine
address of the page for dom0. Therefore we can access memory at physical
address == dma_addr_r handle and perform the cache flushing there. Some
cache maintenance operations require a virtual address. Instead of using
ioremap_cache, that is not safe in interrupt context, we allocate a
per-cpu PAGE_KERNEL scratch page and we manually update the pte for it.
arm64 doesn't need cache maintenance operations on unmap for now.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Tested-by: Denis Schneider <v1ne2go@gmail.com>
The flag tells us that the hypervisor maps a grant page to guest
physical address == machine address of the page in addition to the
normal grant mapping address. It is needed to properly issue cache
maintenance operation at the completion of a DMA operation involving a
foreign grant.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Tested-by: Denis Schneider <v1ne2go@gmail.com>
This patch adds dma support in both sdcc1 and sdcc3 device node.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This patch adds support to SD card controller using generic pl180 mmci driver.
This patch also adds temporary fixed regulator to get it going till the actual
regulator is mainlined.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the mmcc node so that we can probe and use the multimedia
clocks on apq8064.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This patch adds DT support to configure GPIO_78 as function ps_hold
on apq8064.
CC: Rob Herring <robh+dt@kernel.org>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: devicetree@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This patch adds device tree nodes to support pinctrl for apq8064 SOC
CC: Rob Herring <robh+dt@kernel.org>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: devicetree@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This patch adds the TLMM node for the APQ8084 platform.
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add basic support for the IFC6540 single-board computer boards, that are
based on the APQ8084 SoC. This patch adds the initial device tree and the
neccessary nodes required for enabling the serial port and eMMC.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the PMIC and the sub-devices that are currently supported in
the kernel to the DT.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add the PMIC and the sub-devices that are currently supported in
the kernel to the DT.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
The ISS encoding for an exception from a Data Abort has a WnR
bit[6] that indicates whether the Data Abort was caused by a
read or a write instruction. While there are several fields
in the encoding that are only valid if the ISV bit[24] is set,
WnR is not one of them, so we can read it unconditionally.
Instead of fixing both implementations of kvm_is_write_fault()
in place, reimplement it just once using kvm_vcpu_dabt_iswrite(),
which already does the right thing with respect to the WnR bit.
Also fix up the callers to pass 'vcpu'
Acked-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
using LVDS channel 1 on an i.MX53 leads to following error:
imx-ldb 53fa8008.ldb: unable to set di0 parent clock to ldb_di1
This comes from imx_ldb_set_clock with mux = 0. Mux parameter must be "1" for
reparenting di1 clock to ldb_di1. The value of the mux param comes from device
tree port settings.
On i.MX5, the internal two-input-multiplexer is used. Due to hardware limitations,
only one port (port@[0,1]) can be used for each channel (lvds-channel@[0,1],
respectively)
Documentation update suggested by Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Fixes: e05c8c9a79 ("ARM: dts: imx53: Add IPU DI ports and endpoints, move imx-drm node to dtsi")
Cc: <stable@vger.kernel.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
We should be able to talk to the PMIC at 400kHz. No need to talk at
the slow 100kHz.
As measured by ftrace (with a bunch of extra patches, since cpufreq
for rk808 hasn't landed yet):
before this change: cpu0_set_target() => ~500us
after this change: cpu0_set_target() => ~300us
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by Addy Ke <addy.ke@rock-chips.com>
Tested-by Addy Ke <addy.ke@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Make domain_devices[] static __initdata
* Add and use rmobile_add_devices_to_domain
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Merge tag 'renesas-pm-cleanups-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Pull "Renesas ARM Based SoC PM Cleanups for v3.18" from Simon Horman:
* Make domain_devices[] static __initdata
* Add and use rmobile_add_devices_to_domain
Signed-off-by: Arnd Bergmann <ardn@arndb.de>
* tag 'renesas-pm-cleanups-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: armadillo800eva legacy: Use rmobile_add_devices_to_domains()
ARM: shmobile: r8a7740: Clean up pm domain table
ARM: shmobile: r8a7740: Use rmobile_add_devices_to_domains()
ARM: shmobile: sh7372: Make domain_devices[] static __initdata
ARM: shmobile: mackerel: Make domain_devices[] static __initdata
The r8a7794 support is always compiled using ARCH_MULTIPLATFORM which
selects USE_OF. So #ifdef CONFIG_USE_OF is unnecessary.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Support for the r8a7794 was recently added.
Enable it in the shmobile_defconfig to increase build coverage.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
LDO8 regulator is used for act led and serial cosole power supply.
Its DT status is declared as "disabled", however the serial console was
functional until Commit 318dbb02b ("regulator: palmas: Fix SMPS
enable/disable/is_enabled") wich properly turns off LDO8 on boot.
Fix serial cosole power supply (and act led) on boot by turning LDO8 on.
Fixes: 318dbb02b ("regulator: palmas: Fix SMPS enable/disable/is_enabled")
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Tested-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The nand timings were scaled down by 2 to account for
the 2x rate returned by clk_get_rate(gpmc_fclk).
As the clock data got fixed by [1], revert back to actual
timings (i.e. scale them up by 2).
Without this NAND doesn't work on dra7-evm.
[1] - commit dd94324b98
ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates
Fixes: ff66a3c86e ("ARM: dts: dra7: add support for parallel NAND flash")
Cc: <stable@vger.kernel.org> [3.16]
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In the recent change to the reset function API (commit
7b6d864b48), the mode argument changed from a
char to an enum. lpc23xx_restart() only handles REBOOT_SOFT and REBOOT_HARD,
but the new kernel code emits REBOOT_COLD (0) on reboots now which leads to
lpc32xx simply not rebooting (but halting).
This patch fixes this by just resetting unconditionally as on other platforms
(e.g. mach-bcm2835).
Pulling lpc32xx_watchdog_reset() into lpc23xx_restart() since the while() in
lpc23xx_restart() is part of the procedure anyway and lpc32xx_watchdog_reset()
isn't used anywhere else anymore.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Pull "ARM: LPC32xx: Device tree updates" from Roland Stigge:
This enables ubifs in the lpc32xx defconfig.
* 'lpc32xx/defconfig' of git://git.antcom.de/linux-2.6:
ARM: LPC32xx: defconfig update
All the current support of mach-mxt_td60 board can be converted to devicetree.
Remove the board file.
Cc: Alan Carvalho de Assis <acassis@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
OMAP4, OMAP5 and DRA7 share a lot of common logic and data structures.
These have been enabled in the previous patches, however, this also
means that OMAP5 or DRA7 only builds also need to build OMAP4 logic.
Update to reuse OMAP4 logic.
This fixes the 'undefined reference to 'omap4_pm_init_early'' in
OMAP5 or DRA7 only builds.
Fixes: 6af16a1dac ("ARM: DRA7: Add hook in SoC initcalls to enable pm initialization")
Fixes: 628ed47170 ("ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization")
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This enables EMAC Rockchip support on radxa rock boards.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This adds support for EMAC Rockchip driver on RK3188 SoCs.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Reported by Mikulas Patocka, kmemcheck currently barks out a
false positive since we don't have special kmemcheck annotation
for bitfields used in bpf_prog structure.
We currently have jited:1, len:31 and thus when accessing len
while CONFIG_KMEMCHECK enabled, kmemcheck throws a warning that
we're reading uninitialized memory.
As we don't need the whole bit universe for pages member, we
can just split it to u16 and use a bool flag for jited instead
of a bitfield.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: Daniel Borkmann <dborkman@redhat.com>
Acked-by: Alexei Starovoitov <ast@plumgrid.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This is the ARM variant for 314beb9bca ("x86: bpf_jit_comp: secure bpf
jit against spraying attacks").
It is now possible to implement it due to commits 75374ad47c ("ARM: mm:
Define set_memory_* functions for ARM") and dca9aa92fc ("ARM: add
DEBUG_SET_MODULE_RONX option to Kconfig") which added infrastructure for
this facility.
Thus, this patch makes sure the BPF generated JIT code is marked RO, as
other kernel text sections, and also lets the generated JIT code start
at a pseudo random offset instead on a page boundary. The holes are filled
with illegal instructions.
JIT tested on armv7hl with BPF test suite.
Reference: http://mainisusuallyafunction.blogspot.com/2012/11/attacking-hardened-linux-systems-with.html
Signed-off-by: Daniel Borkmann <dborkman@redhat.com>
Signed-off-by: Alexei Starovoitov <ast@plumgrid.com>
Acked-by: Mircea Gherzan <mgherzan@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Currently there is a wild mixture of isl, isil, and intersil
compatibles in the kernel. At this point, changing the vendor
symbol to the most often used variant, which is equal to the
NASDAQ symbol, isil, should not hurt.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lkml.kernel.org/r/1410167960-554-4-git-send-email-p.zabel@pengutronix.de
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Switch the Armada SoC SPI port device tree binding to use the new improved
armada-370-spi compatible name. This allows for a wider range of baud rates
to be used.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1410147029-30067-1-git-send-email-gerg@uclinux.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The bootloader on the Netgear ReadyNAS RN2120 uses Hardware BCH
ECC (strength = 4), while the pxa3xx NAND driver by default uses
Hamming ECC (strength = 1).
This patch changes the ECC mode on these machines to match that
of the bootloader and of the stock firmware. That way, it is
now possible to update the kernel from userland (e.g. using
standard tools from mtd-utils package); u-boot will happily
load and boot it.
The issue was initially reported and fixed by Ben Pedell for
RN102. The RN2120 shares the same Hynix H27U1G8F2BTR NAND
flash and setup. This patch is based on Ben's fix for RN102.
Fixes: ad51eddd95 ("ARM: mvebu: Enable NAND controller in ReadyNAS 2120 .dts file")
Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/61f6a1b7ad0adc57a0e201b9680bc2e5f214a317.1410035142.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The bootloader on the Netgear ReadyNAS RN104 uses Hardware BCH
ECC (strength = 4), while the pxa3xx NAND driver by default uses
Hamming ECC (strength = 1).
This patch changes the ECC mode on these machines to match that
of the bootloader and of the stock firmware. That way, it is
now possible to update the kernel from userland (e.g. using
standard tools from mtd-utils package); u-boot will happily
load and boot it.
The issue was initially reported and fixed by Ben Pedell for
RN102. The RN104 shares the same Hynix H27U1G8F2BTR NAND
flash and setup. This patch is based on Ben's fix for RN102.
Fixes: 0373a558bd ("ARM: mvebu: Enable NAND controller in ReadyNAS 104 .dts file")
Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/920c7e7169dc6aaaa3eb4bced2336d38e77b8864.1410035142.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370 SoC has a Spread Spectrum Clock Generator. This commit
adds the description of this generator to the Device Tree describing
this SoC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Link: https://lkml.kernel.org/r/1409645719-20003-4-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Initial r8a7794 SoC support
* Support Cortex-A7 in shmobile_init_delay()
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Merge tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Third Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
* Initial r8a7794 SoC support
* Support Cortex-A7 in shmobile_init_delay()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Initial r8a7794 SoC support
ARM: shmobile: support Cortex-A7 in shmobile_init_delay()
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Merge tag 'socfpga_update_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next into next/dt
Pull "arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries" From Dinh Nguyen:
5 of the 6 patches are DTS updates and the 1 patch is updating
the MAINTAINERS entry with my new email address.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'socfpga_update_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next:
arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.
ARM: dts: socfpga: memreserve first 4KB for future system use
ARM: dts: socfpga: Add SD card detect
ARM: dts: socfpga: remove extra alias in the ArriaV devkit
ARM: dts: socfpga: unuse the slot-node and deprecate the supports-highspeed for dw-mmc
MAINTAINERS: update entries for ARM/SOCFPGA platform
commit a38b1f60b5 ("ARM: pxa: Add non device-tree timer link to
clocksource") introduced a harmless section mismatch warning for
all pxa platforms, by introducing a new pxa_timer_init() function
that is not marked __init but that calls pxa_timer_nodt_init(),
which is.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Commit 21278aeafb ("ARM: use menuconfig for sub-arch menus") improved
the sub-arch menus, but accidentally caused new warnings for omap1.
This was because the commit added a menu entry around config ARCH_OMAP
bool entry where the menu had depends on ARCH_MULTI_V6 || ARCH_MULTI_V7.
As ARCH_OMAP is shared between omap1 and omap2plus, let's fix the
issue by defining ARCH_OMAP in the shared plat-omap/Kconfig.
Fixes: 21278aeafb ("ARM: use menuconfig for sub-arch menus")
Reported-by: Andreas Ruprecht <rupran@einserver.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Mark rxd as wakeupcapable for 115200n8 no hardware-flow control
configuration. If h/w flow control is being used, then rts/cts
appropriately should be used.
Signed-off-by: Nishanth Menon <nm@ti.com>
We've had deeper idle states working on omaps for few years now,
but only in the legacy mode. When booted with device tree, the
wake-up events did not have a chance to work until commit
3e6cee1786 ("pinctrl: single: Add support for wake-up interrupts")
that recently got merged. In addition to that we also needed
commit 79d9701559 ("of/irq: create interrupts-extended property")
that's now also merged.
Note that there's no longer need to specify the wake-up bit in
the pinctrl settings, the request_irq on the wake-up pin takes
care of that.
Signed-off-by: Nishanth Menon <nm@ti.com>
Now that ti,am437-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark the pinctrl as interrupt controller so that it can
be used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon <nm@ti.com>
Now that ti,dra7-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be used
with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon <nm@ti.com>
Now that ti,omap5-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be
used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon <nm@ti.com>
This adds initial support. For now, regulators are always on and we
don't specify the input supply for all of the regulators.
Signed-off-by: huang lin <hl@rock-chips.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
It's convenient (and less confusing to people reading logs) if the
eMMC port on rk3288 is consistenly marked with mmc0 and the sdmmc port
on rk3288 is consistently marked with mmc1. Add the appropriate
aliases.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds basic SPI nodes to the base rk3288 device tree file.
A few notes:
* It's assumed that most users of the SPI ports are using chip select
0. Thus the default pinctrl for the ports enables chip select 0
(but not chip select 1 on ports that have it). If a board wants to
use chip select 1 or wants a GPIO chip select the board should
override the pinctrl (just like boards can override UART pinctrl if
they have hardware flow control).
* Since SPI DMA support appears broken and the SPI works fine without
DMA we don't include the DMA references. That can come in a later
change.
Signed-off-by: huang lin <hl@rock-chips.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
USB host1 port is the host A port nearby the otg port.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7740 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7779 TMU
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7791 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r7s72100 MTU2
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7790 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
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Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' into dt-timers-for-v3.18
Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
Use a table and the rmobile_add_devices_to_domains() helper function to
add all platform devices to their power domains at once, which is more
size-efficient than calling rmobile_add_device_to_domain() explicitly
for all devices individually.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- Sort pm domains by bit_shift value,
- Combine closing and opening curly braces on a single line, as the
table will grow much bigger soon.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use a table and the rmobile_add_devices_to_domains() helper function to
add all platform devices to their power domains at once, which is more
size-efficient than calling rmobile_add_device_to_domain() explicitly
for all devices individually.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Make the domain_devices[] array static and __initdata, to reduce kernel
size:
- Making it static gets rid of the code to copy the data to the stack,
- Marking it __initdata allows more init memory to be freed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Make the domain_devices[] array static and __initdata, to reduce kernel
size:
- Making it static gets rid of the code to copy the data to the stack,
- Marking it __initdata allows more init memory to be freed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OPP is now a normal kernel library selected by its users rather than a
feature that architectures need to enable so ARCH_HAS_OPP serves no
function any more - remove the selects.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add regulator-name properties for the regulators that don't have them,
allowing the kernel to display the name from the schematic rather than
the name of the regulator on the PMIC in order to improve diagnostics.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
CM-T54 CoM can be used with various custom baseboards, other
than SB-T54 (supplied with SBC-T54 single board computer).
Update model property of SBC-T54 DT to clarify this.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The RFBI node for OMAP DSS was left out when adding the rest of the DSS
nodes, because it was not clear how to set up the clocks for the RFBI.
However, it seems that if there is a HWMOD for a device, we also need a
DT node for it. Otherwise, at boot, we get:
WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2542 _init+0x464/0x4e0()
omap_hwmod: dss_rfbi: doesn't have mpu register target base
Now that v3.17-rc3 contains a fix 8fd46439e1 ("ARM: dts:
omap54xx-clocks: Fix the l3 and l4 clock rates") for the L3 ICLK
required by the RFBI, let's add the RFBI node to get rid of the
warning.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
[tony@atomide.com: updated description per comments from Nishant]
Signed-off-by: Tony Lindgren <tony@atomide.com>
These baseboards are equipped with the Technexion TAO35030 SOM. So
they include this dtsi. The common parts are extracted into an "common"
dtsi file. The main difference between both boards is, that the *lcd
has DSS support enabled for the LCD.
Some HEAD acoustics specific features are:
- LED handling
- Special FPGA/DSP audio driver (not included in this series)
- powerdown GPIO
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This baseboard is equipped with the Technexion TAO35030 SOM. So
includes this dtsi. Some Thunder specific features are:
- LCD panel
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Technexion TAO3530 is a OMAP3530 based SOM. This patch adds the
basic support for it as an dtsi file which can be included by
baseboard equipped with this SOM. E.g. the Technexion Thunder
baseboard.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Set internal clock source for MMC2 on tao3530.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM57xx processor family are variants of DRA7 family of processors and
targetted at industrial and non-automotive applications.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA72x-evm uses TPS65917 PMIC. Add the node.
NOTE: LDO2 is actually unused, but the usage if any is expected to be
between 1.8 to 3.3v IO voltage. So define the node.
NOTE: Interrupt used is crossbar number based.
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
I2C1 bus is used for the following peripherals
P8 connector (MLB)
TLV320AIC3106 Audio codec
J15 LCD header
24WC256 eeprom
TMP102AIDRLT temperature sensor
PCF8575 GPIO expander
PCA9306 i2c voltage translator -> Goes to P9 for comm interface
P2 expansion connector
TPS65917 PMIC
The slowest speed of all the peripherals seems to be 400KHz.
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: minor modifications]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Since genpd at late init, will try to disable unused PM domains we
don't need to do it from the machine specific code as well.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Since genpd at late init, will try to disable unused PM domains we
don't need to do it from here as well.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The dev_irq_safe configuration is redundant, genpd don't have any
special treatmeant for handling it. Let's remove it.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The dev_irq_safe configuration is redundant, genpd don't have any
special treatmeant for handling it. Let's remove it.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
NOTE: the hardware was originally designed to be capable of achieving
deep power states such as OFF and OSWR, however due to various issues
and risks, deepest valid state was determined to be CSWR - hence we use
the errata framework to handle this case.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: split this out of original code and isolate it]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the
OMAP5 and DRA7 family of processors.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor consolidation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: conflict resolution, dra7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Not all SoCs support OFF mode - for example DRA74/72. So, use valid
power state during CPU hotplug.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
We are using power domain state as RET and logic state as OFF. This
state is OSWR. This may not always be supported on ALL power domains. In
fact, on certain power domains, this might result in a hang on certain
platforms. Instead, depend on powerdomain data to provide accurate
information about the supported powerdomain states and use the
appropriate function to query and use it as part of suspend path.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Move the logic state as different for each power domain. This allows us
to customize the deepest power state we should target over all for each
powerdomain in the follow on patches.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
powerdomain configuration in OMAP is done using PWRSTCTRL register for
each power domain. However, PRCM lets us write any value we'd like to
the logic and power domain target states, however the SoC integration
tends to actually function only at a few discrete states. These valid
states are already in our powerdomains_xxx_data.c file.
So, provide a function to easily query valid low power state that the
power domain is allowed to go to.
Based on work originally done by Jean Pihet <j-pihet@ti.com>
https://patchwork.kernel.org/patch/1325091/ . There is no attempt to
create a new powerdomain solution here, except fixing issues seen
attempting invalid programming attempts. Future consolidation to the
generic powerdomain framework should consider this requirement as
well.
Similar solutions have been done in product kernels in the past such
as:
https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
No need to invoke callback when the clkdm pointer is NULL.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Update the power domain power states for final production chip
capability. OFF mode, OSWR etc have been descoped for various domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Allow the PRM interrupt information to be picked up from device tree.
OMAP3 may use legacy boot and needs to be compatible with old dtbs
(without interrupt populated), for these, we use the value which is
pre-populated.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP5 and DRA7 can now use pinctrl based I/O daisychain wakeup
capability. So, enable the support.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
"wkup" event at bit offset 0 exists only on OMAP3.
OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU
register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3.
The same applies to AM437x as well.
Remove the wrong definition.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Allow the PRM interrupt information to be picked up from device tree.
the only exception is for OMAP4 which uses values pre-populated and allows
compatibility with older dtb.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
use the generic function to pick up the prm_instance for a generic logic
which can be reused from OMAP4+
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
PRM device instance can vary depending on SoC. We already handle the
same during reset of the device, However, this is also needed
for other logic instances. So, first abstract this out to a generic
function.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Alexander Bersenev <bay@hackerdom.ru>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Oliver Schinagl <oliver@schinagl.nl>
Acked-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm fixes from Paolo Bonzini:
"A smattering of bug fixes across most architectures"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
powerpc/kvm/cma: Fix panic introduces by signed shift operation
KVM: s390/mm: Fix guest storage key corruption in ptep_set_access_flags
KVM: s390/mm: Fix storage key corruption during swapping
arm/arm64: KVM: Complete WFI/WFE instructions
ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU
KVM: s390/mm: try a cow on read only pages for key ops
KVM: s390: Fix user triggerable bug in dead code
by way of GPIO descriptors, avoiding any use of the GPIO
global numberspace.
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Merge tag 'integrator-for-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc
Merge "single Integrator patch" from Linus Walleij:
This sets up the dynamically detected IM-PD1 GPIO lines
by way of GPIO descriptors, avoiding any use of the GPIO
global numberspace.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'integrator-for-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: add MMCI device to IM-PD1
- a dependency needed for SPI flash
- enable sound on DT platforms
- cleanup of current defconfigs:
- addition of new PWM subsystem and related drivers
- addition of ADC/touchscreen, watchdog or USB depending on the SoC
- addition of power/reset drivers activated during this development cycle
- removal of obsolete config options
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Merge tag 'at91-defconfig' of git://github.com/at91linux/linux-at91 into next/defconfig
Pull "First batch of AT91 defconfig update for 3.18" from Nicolas Ferre:
- a dependency needed for SPI flash
- enable sound on DT platforms
- cleanup of current defconfigs:
- addition of new PWM subsystem and related drivers
- addition of ADC/touchscreen, watchdog or USB depending on the SoC
- addition of power/reset drivers activated during this development cycle
- removal of obsolete config options
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-defconfig' of git://github.com/at91linux/linux-at91:
ARM: at91: sama5: update defconfig
ARM: at91: at91sam9rl: update defconfig
ARM: at91: at91sam9g45: update defconfig
ARM: at91: at91sam9263: update defconfig
ARM: at91: at91sam9261_9g10: update defconfig
ARM: at91: at91sam9260_9g20: update defconfig
ARM: at91: at91_dt: update defconfig
ARM: at91/sama5_defconfig: enable sound support
ARM: at91/at91_dt_defconfig: enable sound support
ARM: at91: add MTD_SPI_NOR (new dependency for M25P80)
- 2 little fixes for at91sam9x5 and at91sam9n12ek
- removal of a board specific hook for sama5d3xek about phy fixup
replaced with proper DT property definition.
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Merge tag 'at91-dt2' of git://github.com/at91linux/linux-at91 into next/dt
Pull "Second batch of AT91 DT patches for 3.18" from Nicolas Ferre:
- 2 little fixes for at91sam9x5 and at91sam9n12ek
- removal of a board specific hook for sama5d3xek about phy fixup
replaced with proper DT property definition.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-dt2' of git://github.com/at91linux/linux-at91:
ARM: at91: remove phy fixup for sama5d3xek boards
ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards
ARM: at91/dt: sam9n12ek: ohci: add port and vbus property
ARM: at91/dt: sam9x5: fix ADC compatible string
- reset, poweroff and ram drivers are moved to their proper
location instead of being in mach-at91 directory. They now use
the appropriate frameworks.
- big amount of removal of these machine specific drivers and use
of the newly created drivers. This lead to an overhaul of the setup.c AT91
startup code.
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Merge tag 'at91-drivers' of git://github.com/at91linux/linux-at91 into next/drivers
Merge "First batch of AT91 drivers for 3.18" from Nicolas Ferre:
- reset, poweroff and ram drivers are moved to their proper
location instead of being in mach-at91 directory. They now use
the appropriate frameworks.
- big amount of removal of these machine specific drivers and use
of the newly created drivers. This lead to an overhaul of the setup.c AT91
startup code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-drivers' of git://github.com/at91linux/linux-at91: (31 commits)
power: reset: at91-poweroff: fix wakeup status register index
ARM: at91/power/reset: fix Kconfig "depends on" directive
ARM: at91: fix ramc standby function registration
ARM: at91: Remove rstc and shdwc headers
ARM: at91: Remove rstc and shdwnc global base addresses
ARM: at91/pm: Remove show_reset_status function
ARM: at91: Remove poweroff code
ARM: at91: Register the poweroff driver
ARM: at91: Remove poweroff DT probing
ARM: at91: Remove reset code from the machine code
ARM: at91: Call at91_register_devices in the board files
ARM: at91: Probe the reset driver
ARM: at91/soc: Introduce register_devices callback
ARM: at91: Remove the old-style reset probing
ARM: at91: Rework ramc mapping code
ARM: at91: setup: Switch to pr_fmt
ARM: at91: remove old irq material
ARM: at91: make use of the new AIC driver for dt enabled boards
ARM: at91: enclose at91_aic_xx calls in IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks
ARM: at91: introduce OLD_IRQ_AT91 Kconfig option
...
Following the merge of AIC/AIC5 code as standard irqchip drivers during early
3.17 merge window, we can use these drivers for AT91 DT-enabled chips and
boards.
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Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
Merge "at91: cleanup for 3.18" from Nicolas Ferre:
First batch of AT91 cleanup for 3.18:
Following the merge of AIC/AIC5 code as standard irqchip drivers during early
3.17 merge window, we can use these drivers for AT91 DT-enabled chips and
boards.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-cleanup' of git://github.com/at91linux/linux-at91:
ARM: at91: remove old irq material
ARM: at91: make use of the new AIC driver for dt enabled boards
ARM: at91: enclose at91_aic_xx calls in IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks
ARM: at91: introduce OLD_IRQ_AT91 Kconfig option
With eBPF getting more extended and exposure to user space is on it's way,
hardening the memory range the interpreter uses to steer its command flow
seems appropriate. This patch moves the to be interpreted bytecode to
read-only pages.
In case we execute a corrupted BPF interpreter image for some reason e.g.
caused by an attacker which got past a verifier stage, it would not only
provide arbitrary read/write memory access but arbitrary function calls
as well. After setting up the BPF interpreter image, its contents do not
change until destruction time, thus we can setup the image on immutable
made pages in order to mitigate modifications to that code. The idea
is derived from commit 314beb9bca ("x86: bpf_jit_comp: secure bpf jit
against spraying attacks").
This is possible because bpf_prog is not part of sk_filter anymore.
After setup bpf_prog cannot be altered during its life-time. This prevents
any modifications to the entire bpf_prog structure (incl. function/JIT
image pointer).
Every eBPF program (including classic BPF that are migrated) have to call
bpf_prog_select_runtime() to select either interpreter or a JIT image
as a last setup step, and they all are being freed via bpf_prog_free(),
including non-JIT. Therefore, we can easily integrate this into the
eBPF life-time, plus since we directly allocate a bpf_prog, we have no
performance penalty.
Tested with seccomp and test_bpf testsuite in JIT/non-JIT mode and manual
inspection of kernel_page_tables. Brad Spengler proposed the same idea
via Twitter during development of this patch.
Joint work with Hannes Frederic Sowa.
Suggested-by: Brad Spengler <spender@grsecurity.net>
Signed-off-by: Daniel Borkmann <dborkman@redhat.com>
Signed-off-by: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Kees Cook <keescook@chromium.org>
Acked-by: Alexei Starovoitov <ast@plumgrid.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The defined mechanism for programming the Tegra pinmux is to perform all
of the following at once in order, before using any I/O controller that
is affected by the pinmux:
- Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit.
- Set up any GPIO pins to their "initial" state.
- Program all pinmux settings in one go.
Other methods such as:
- Not setting CLAMP_INPUTS_WHEN_TRISTATED.
- Not setting GPIOs to their "initial" state before programming the
pinmux settings of the related pin, in particular the mux function.
- Not programming the entire pinmux at once, in order to avoid
possible conflicting settings.
... are not qualified or supported by NVIDIA ASIC/syseng. They could
cause glitches or undesired output levels on some pins, or controller
malfunction.
While we've been getting away with doing something different on many
Tegra boards without issue, I believe we've just been getting lucky.
I'd like to switch all Tegra124 systems to the correct scheme now so
they provide the right example to follow, and require that any new
boards we support upstream work in the same fashion.
While it would be nice to update boards containing older SoCs for
consistency, I don't anticipate doing so. It's too much churn to change
at this time. At least with all Tegra124 boards converted, the most
recent boards provide the correct example.
Since the bootloader needs to reprogram the pinmux to access certain
peripherals, it must program the entire pinmux due to the supported
rules above. As such, there is no need to program any part of the pinmux
from the kernel, unless dynamic pinmuxing is used. Given this, we couuld
simply remove the pinmux "default" state from the DT entirely. However,
some bootloaders parse the DT to perform their initial pinmux setup, so
it's useful to keep the pinmux data in DT. To allow this while avoiding
redundant work in the kernel, rename the "default" state to "boot". The
kernel won't apply this, but bootloaders can still look for this state
name and apply it. Note however that the DT provides zero information
about the required initial GPIO setup, so bootloaders using this approach
are not likely to operate correctly without an additional GPIO
initialization table somewhere. Previous discussions on the DT mailing
list have rejected adding such a table to DT...
The following U-Boot commits fully initialize the pinmux:
Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1
Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates
Both are part of U-Boot v2014.07 and later.
Without those commits, the only fallout I see from this change is that
HDMI on Venice2 no longer works. Given the very small user-base of this
platform, I feel that requiring a bootloader update is reasonable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
processor and is similar to the Venice2 reference platform.
The keyboard, USB 2, audio, sdcard and emmc have been tested
and work on the 1366x768 models. The Full HD models haven't been
tested yet.
WiFi does not yet work, it needs at least some PMIC changes to enable
the 32k clock.
The elan trackpad is not yet functional but hopefully will be soon as
there are patches under review.
There is also an issue on reboot because the TPM isn't reset. It will
cause the stock firmware to enter recovery mode. This can be worked
around by an EC-reset, press the refresh and power keys at the same
time.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
These labels will be used by other boards in addition to Venice2, move
them to tegra124.dtsi so they are defined in a common place.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Enable timers using DT when booting boards without Legacy-C code
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Merge tag 'renesas-dt-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman:
* Enable timers using DT when booting boards without Legacy-C code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-dt-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: genmai-reference: Enable MTU2 in device tree
ARM: shmobile: r7s72100: Add MTU2 device to DT
ARM: shmobile: marzen-reference: Enable TMU0 in device tree
ARM: shmobile: koelsch-reference: Enable CMT0 in device tree
ARM: shmobile: lager-reference: Enable CMT0 in device tree
ARM: shmobile: r8a7779: Add TMU devices to DT
ARM: shmobile: r8a7791: Add CMT devices to DT
ARM: shmobile: r8a7790: Add CMT devices to DT
Conflicts:
arch/arm/mach-shmobile/setup-r8a7779.c
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
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Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18" from Simon Horman:
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740: Remove r8a7740_add_standard_devices_dt
ARM: shmobile: armadillo800eva-reference: Do not use r8a7740_add_standard_devices_dt()
ARM: shmobile: armadillo800eva-reference: Enable CMT1 in device tree
ARM: shmobile: r8a7740: Add CMT1 device to DT
ARM: shmobile: armadillo800eva-reference: add clock overrides to DTS
ARM: shmobile: r8a7740: add MSTP clock assignments to DT
ARM: shmobile: r8a7740: add SoC clocks to DTS
ARM: shmobile: r8a7740: clock register bits
The atmel,clk-divisors property is taking 4 divisors, if less are
provided, the clock registration will fail.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Actually register clocks from device tree when using the common clock
framework.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: add at91 to function name]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The at91sam9g20 SOC uses its own pllb implementation which is different
from the one inherited from at91sam9260 SOC.
Signed-off-by: Gaël PORTAY <gael.portay@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* Use shmobile_init_delay across a wider range of SoCs
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Merge tag 'renesas-init-delay-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Init Delay Updates For v3.18" from Simon Horman:
* Use shmobile_init_delay across a wider range of SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-init-delay-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g: Use shmobile_init_delay()
ARM: shmobile: bockw: Use shmobile_init_delay()
ARM: shmobile: r8a7778: Use shmobile_init_delay()
ARM: shmobile: sh73a0: Use shmobile_init_delay()
ARM: shmobile: Remove shmobile_setup_delay()
ARM: shmobile: r8a73a4: Use shmobile_init_delay()
ARM: shmobile: sh7372: Use shmobile_init_delay()
ARM: shmobile: r8a7778: Update DTS to include CPU frequency
ARM: shmobile: sh73a0: Update DTS to include CPU frequency
ARM: shmobile: sh7372: Update DTS to include CPU frequency
ARM: shmobile: kzm9g-reference: Remove unneeded nr_irqs initialization
ARM: shmobile: kzm9g: Remove unneeded nr_irqs initialization
ARM: shmobile: marzen: Remove NR_IRQS_LEGACY
ARM: shmobile: ape6evm: Use shmobile_init_delay()
ARM: shmobile: ape6evm: Add shmobile_init_late()
ARM: shmobile: bockw: Add shmobile_init_late()
ARM: shmobile: marzen: Add shmobile_init_late()
ARM: shmobile: kzm9g: Add shmobile_init_late()
properly on the new am437x and dra7 hardware for several devices
such as I2C, NAND, DDR3 and USB. There's also a clock fix for omap3.
And also included are two minor cosmetic fixes that are not
stictly fixes for the new hardware support added recently to
downgrade a GPMC warning into a debug statement, and fix the
confusing comments for dra7-evm spi1 mux.
Note that these are all .dts changes except for a GPMC change.
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Merge tag 'omap-fixes-against-v3.17-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "omap fixes against v3.17-rc3" from Tony Lindgren:
Few fixes for omaps mostly for various devices to get them working
properly on the new am437x and dra7 hardware for several devices
such as I2C, NAND, DDR3 and USB. There's also a clock fix for omap3.
And also included are two minor cosmetic fixes that are not
stictly fixes for the new hardware support added recently to
downgrade a GPMC warning into a debug statement, and fix the
confusing comments for dra7-evm spi1 mux.
Note that these are all .dts changes except for a GPMC change.
* tag 'omap-fixes-against-v3.17-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (255 commits)
ARM: dts: dra7-evm: Add vtt regulator support
ARM: dts: dra7-evm: Fix spi1 mux documentation
ARM: dts: am43x-epos-evm: Disable QSPI to prevent conflict with GPMC-NAND
ARM: OMAP2+: gpmc: Don't complain if wait pin is used without r/w monitoring
ARM: dts: am43xx-epos-evm: Don't use read/write wait monitoring
ARM: dts: am437x-gp-evm: Don't use read/write wait monitoring
ARM: dts: am437x-gp-evm: Use BCH16 ECC scheme instead of BCH8
ARM: dts: am43x-epos-evm: Use BCH16 ECC scheme instead of BCH8
ARM: dts: am4372: fix USB regs size
ARM: dts: am437x-gp: switch i2c0 to 100KHz
ARM: dts: dra7-evm: Fix 8th NAND partition's name
ARM: dts: dra7-evm: Fix i2c3 pinmux and frequency
Linux 3.17-rc3
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
* Enable Armadillo 800 EVA board in multiplatform defconfig
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Merge tag 'renesas-defconfig3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/defconfig
Pull "Renesas ARM Based SoC Defconfig Updates for v3.18" from Simon Horman:
Third Round of Renesas ARM Based SoC Defconfig Updates for v3.18
* Enable Armadillo 800 EVA board in multiplatform defconfig
Second Round Of Renesas ARM Based SoC Defconfig Updates For v3.18
* Do not disable SUSPEND in Bockw defconfig
- Suspend to ram is now supported
Renesas ARM Based SoC Defconfig Updates for v3.18
* Enable initrd in shmobile defconfig
* Enable missing hardware support in shmobile and several board defconfigs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-defconfig3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable Armadillo 800 EVA board in multiplatform defconfig
ARM: shmobile: bockw: Do not disable SUSPEND in defconfig
ARM: shmobile: defconfig: enable initrd
ARM: shmobile: marzen_defconfig: Enable missing hardware support
ARM: shmobile: lager_defconfig: Enable missing hardware support
ARM: shmobile: kzm9g_defconfig: Enable missing hardware support
ARM: shmobile: koelsch_defconfig: Enable missing hardware support
ARM: shmobile: bockw_defconfig: Enable missing hardware support
ARM: shmobile: ape6evm_defconfig: Enable missing hardware support
ARM: shmobile: shmobile_defconfig: Enable missing hardware support
* Update name of "R-Car M2-W" SoC (previously there was no "-W")
* Consolidate Legacy SH_CLK_CPG and CPU_V7 Kconfig
* Only select PM_RMOBILE for legacy case
* Cleanup pm-rcar.o and pm-rmobile.o build using Kconfig
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Merge tag 'renesas-kconfig-cleanups-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Pull "Renesas ARM Based SoC Kconfig Cleanups for v3.18" from Simon Horman:
* Update name of "R-Car M2-W" SoC (previously there was no "-W")
* Consolidate Legacy SH_CLK_CPG and CPU_V7 Kconfig
* Only select PM_RMOBILE for legacy case
* Cleanup pm-rcar.o and pm-rmobile.o build using Kconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-kconfig-cleanups-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791 is now called "R-Car M2-W"
ARM: shmobile: Consolidate Legacy SH_CLK_CPG Kconfig
ARM: shmobile: Consolidate Legacy CPU_V7 Kconfig
ARM: shmobile: Only select PM_RMOBILE for legacy case
ARM: shmobile: Cleanup pm-rmobile.o build using Kconfig
ARM: shmobile: Cleanup pm-rcar.o build using Kconfig
ARM: shmobile: Introduce a Kconfig entry for R-Car Gen2
ARM: shmobile: Introduce a Kconfig entry for R-Car Gen1
ARM: shmobile: Introduce a Kconfig entry for R-Mobile
Includes an update to 3.17-rc2 to avoid a dependency
The Kconfig symbol PLAT_SPEAR_SINGLE briefly appeared during the v3.10
development cycle. It was removed in a merge commit before v3.10. A few
references to it were left in the tree, probably because they didn't
generate merge conflicts. Whatever it was, they're useless now and can
safely be removed.
Reported-by: Martin Walch <walch.martin@web.de>
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Reviewed-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Cc: Rajeev Kumar <rajeev_kumar@mentor.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The SAMA5 and SAM9x5 series both have drive strength
options for the PIOs. This patch adds the ability to set
one of three hardware options for drive strengths of low,
medium or high for the each pin. The actual current output
of the chip based on the setting is defined in the datasheets
and varies per pins separate from banks and with supply
voltage.
This patch adds three new dt-bindings that allow setting the
strength when configuring pins. By default, no change will
be made to the drive strength of a pin from its reset value.
Due to the difference between the register addresses of the
SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added.
Signed-off-by: Marek Roszko <mark.roszko@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Initial support for the r8a7794 SoC, based on work by Hisashi Nakamura.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The kernel panic occurs when running an allmodconfig kernel on
OMAP4460. The inicall "cns3xxx_pcie_init" does not check which
hardware it's running on and just tries to access to its specific
registers. Now call it from .init_late callback from the two
machine descriptors.
Signed-off-by: Xia Kaixu <kaixu.xia@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Anton Vorontsov <anton@enomsg.org>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: linaro-kernel@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Many boards share the cpufreq-cpu0 driver meaning that if we enable it in
multi_v7_defconfig we can get a reasonable amount of functional utility for
systems and test coverage for a fairly small increase in kernel size.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The virtual consumer is a test device intended to be used while developing
regulator drivers, it should never be used in production. Remove it from
all defconfigs to avoid confusion among users.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
on DA850.
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Merge tag 'davinci-fixes-for-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into fixes
This patch fixes setup of second EDMA channel controller
on DA850.
* tag 'davinci-fixes-for-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: edma: Fix configuration parsing for SoCs with multiple eDMA3 CC
DRA7 evm REV G and later boards uses a vtt regulator for DDR3
termination and this is controlled by gpio7_11. This gpio is
configured in boot loader. gpio7_11, which is only available only on
Pad A22, in previous boards, is connected only to an unused pad on
expansion connector EXP_P3 and is safe to be muxed as GPIO on all
DRA7-evm versions (without a need to spin off another dts file).
Since gpio7_11 is used to control VTT and should not be reset or kept
in idle state during boot up else VTT will be disconnected and DDR
gets corrupted. So, as part of this change, mark gpio7 as no-reset and
no-idle on init.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
While auditing the various pin ctrl configurations using the following
command:
grep PIN_ arch/arm/boot/dts/dra7-evm.dts|(while read line;
do
v=`echo "$line" | sed -e "s/\s\s*/|/g" | cut -d '|' -f1 |
cut -d 'x' -f2|tr [a-z] [A-Z]`;
HEX=`echo "obase=16;ibase=16;4A003400+$v"| bc`;
echo "$HEX ===> $line";
done)
against DRA75x/74x NDA TRM revision S(SPRUHI2S August 2014),
documentation errors were found for spi1 pinctrl. Fix the same.
Fixes: 6e58b8f1da ("ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add SOC BUS support with CPU family, machine name and unique ID.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
