The MIPI clock parenting is made in dts file, causing the MIPI clocks to
be parented even if that specific MIPI node is needed or not, causing
issues to the LVDS block (which has a shared PHY with MIPI on 8QXP).
In order to avoid these problems with the shared PHY on 8QXP, store the
MIPI parent clock for phy and escape clocks, along with their rates and
do the re-parenting in the MIPI driver only when a bridge (or panel) is
attached to it.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
[Aisheng: Tested on MX8QM/QXP with single LVDS-HDMI or MIPI panel]
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 2f794bb2f88e18e43dab31f2edea98177fce4e95)
By default, the MIPI RX and TX clocks are parented to the BYPASS clock,
but it seems that this doesn't work on QXP. Since these clocks can also
be parented to MIPI_PLL and MIPI_PLL_DIV2, use the MIPI_PLL_DIV2 with a
fixed rate of 432M and parent the RX and TX clocks to it.
This works on both QM and QXP.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The spec tells us that the CSR start address is 0x1000 and end address
is 0x1FFF according to the subsystem start address. However, it turns
out some space are inaccessible, which would accidently cause system
hang via kernel regmap debugfs. This patch corrects the MIPI CSR
start address and chooses a sensible size, which makes sure all exposed
registers are accessible.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Robert Chiras