Synaptics_dsx touch is on i2c3 bus, so add it here, but default disbale
it, because it share the irq pin with screen, will enable it in the
fsl-imx8mq-evk-dcss-rm67191.dts
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Image subsystem of imx8qm, qxp have some common part and some different
part. For qm, img ss include ISI, CSI0 and CSI1. For qxp, img ss include
ISI, CSI0 and PI0. So split two dtsi file to disable the unrelated modules
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Add focaltech new touch panel ft5426 support.
Set the ft5426 as default panel for dts. If want to use the old panel, then
it needs to boot with imx7ulp-evk-ft5416.dtb file.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Change the reset gpio polarity for RM67191 panel to active low
to match the RM67191 dt bindings file:
'Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt'.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
SDIO wifi and sd1 slot share one usdhc, this patch add sd1 slot support
on imx7ulp evk board, need to do hardware rework first.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Add emmc support for imx6sx-sdb board, due to this support
need remove sd4 sd card slot and solder an eMMC chip, so
this patch add imx6sx-sdb-emmc.dts file.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Add imx6qdl-sabreauto board uart3 DTE pad set. To avoid a flood of
dts files, there comment out DTE pinctrl set. If user want to test
DTE mode, it needs to rebuild the DTB file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit dc6028b08c6bd718d57866a1714f3977ba7820d3)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Add uart5 DTE mode pinctrl set for imx6q-sabresd board. Since there
have pin confliction, so add new dts file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit d63b40d5b1b05992d2328ef0bdc80ec5d96f2dce)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Tuning MMDC ZQ_PU_OFFSET impact DDR IO timing like the value is greater
than 0x9 causing enet lost packets due to the worse timing. Reinforce
ENET DDR IO drive strength can fix the issue. Use the default pin setting
can match the RGMII timing for AI board.
Worse timing cause performance drop, the performance has no drop after
enhancing the DDR IO pins drive strength. Pass over night test.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 5ceb746c0358c0851187a3f4f6f61d02e951eae0)
Conflicts:
arch/arm/boot/dts/imx6qp-sabreauto.dts
(cherry picked from commit 0ea975d4bd6fb8ee479333441e7693a1a1f0d76a)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Add uart4 DCE and DTE pinctrl set. Since there have pin confliction,
so add new dts file. To avoid a flood of dts files, there comment out
DTE pinctrl set. If user want to test DTE mode, it needs to rebuild
the DTB file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit a3602fa5796bb86ba432474220389ec712bde92a)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
The current enet RGMII TXCLK rise/fall time which could be
observed(~0.85ns) is longer than requirement (<=0.75ns).
The current setting, SPEED/DSE/SRE=10/110/1 is used, and then it needs to
increase DSE to 111 "37 Ohm @ 3.3V, 21 Ohm@1.8V, 34 Ohm for DDR".
After the change RGMII TXCLK match the spec requirement.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Add imx6sx-sdb baord uart5 DTE pad set. To avoid a flood of dts files,
there only comment out DTE pinctrl set. If user want to test DTE mode,
it needs to rebuild the DTB file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Add clock parents and rates for enet_axi and enet_phy in dts via
the asigned-parents and assigned-rates attributes.
These were previously set in the ccm driver via set_parent/set_rate
calls but that has been removed in upstream linux.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
-74LV595 function compatible with 74HC595, add 74HC595
driver into imx7d sdb dts.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
This was also added upstream, only change that remains is adding
registers-default on the gpio-expander node.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
IMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.
IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.
Update copyright information.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Currently, all DPUs in i.MX8qm/qxp have the same clocks - pll0/1,
bypass0 and disp0/1. So add the common clocks in imx8-ss-dc0/1.dtsi.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Haibo Chen