Dinh Nguyen 14c79ef213 clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk ... commit b02cf0c473 upstream. The fixed divider the emac_ptp_free_clk should be 2, not 4. Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for Stratix10 platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200831202657.8224-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-10-07 08:01:24 +02:00
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Makefile	clk: socfpga: stratix10: add clock driver for Stratix10 platform	2018-04-06 10:12:35 -07:00
clk-gate-a10.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-gate-s10.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-gate.c	clk: socfpga: deindent code to proper indentation	2019-08-16 10:20:07 -07:00
clk-periph-a10.c	clk: socfpga: Don't reference clk_init_data after registration	2019-08-16 10:20:07 -07:00
clk-periph-s10.c	clk: socfpga: stratix10: fix rate caclulationg for cnt_clks	2019-08-14 09:23:21 -07:00
clk-periph.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
clk-pll-a10.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-pll-s10.c	clk: stratix10: use do_div() for 64-bit calculation	2020-10-01 13:17:33 +02:00
clk-pll.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
clk-s10.c	clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk	2020-10-07 08:01:24 +02:00
clk.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13	2019-05-21 11:28:45 +02:00
clk.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
stratix10-clk.h	clk: socfpga: stratix10: add clock driver for Stratix10 platform	2018-04-06 10:12:35 -07:00