![Bin Liu](/assets/img/avatar_default.png)
Only start the otg_timer in dual role mode; otherwise in peripheral mode when musb is disconnected from the host port, otg_timer starts and continuously toggles the session, which causes VBUS pulse. Signed-off-by: Bin Liu <b-liu@ti.com> Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
759 lines
20 KiB
C
759 lines
20 KiB
C
/*
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* Texas Instruments DSPS platforms "glue layer"
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*
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* Copyright (C) 2012, by Texas Instruments
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*
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* Based on the am35x "glue layer" code.
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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* musb_dsps.c will be a common file for all the TI DSPS platforms
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* such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
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* For now only ti81x is using this and in future davinci.c, am35x.c
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* da8xx.c would be merged to this file after testing.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/pm_runtime.h>
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#include <linux/module.h>
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#include <linux/usb/usb_phy_gen_xceiv.h>
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#include <linux/platform_data/usb-omap.h>
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#include <linux/sizes.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/usb/of.h>
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#include "musb_core.h"
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static const struct of_device_id musb_dsps_of_match[];
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/**
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* avoid using musb_readx()/musb_writex() as glue layer should not be
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* dependent on musb core layer symbols.
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*/
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static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)
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{ return __raw_readb(addr + offset); }
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static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)
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{ return __raw_readl(addr + offset); }
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static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)
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{ __raw_writeb(data, addr + offset); }
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static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
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{ __raw_writel(data, addr + offset); }
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/**
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* DSPS musb wrapper register offset.
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* FIXME: This should be expanded to have all the wrapper registers from TI DSPS
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* musb ips.
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*/
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struct dsps_musb_wrapper {
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u16 revision;
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u16 control;
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u16 status;
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u16 epintr_set;
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u16 epintr_clear;
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u16 epintr_status;
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u16 coreintr_set;
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u16 coreintr_clear;
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u16 coreintr_status;
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u16 phy_utmi;
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u16 mode;
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u16 tx_mode;
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u16 rx_mode;
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/* bit positions for control */
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unsigned reset:5;
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/* bit positions for interrupt */
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unsigned usb_shift:5;
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u32 usb_mask;
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u32 usb_bitmap;
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unsigned drvvbus:5;
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unsigned txep_shift:5;
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u32 txep_mask;
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u32 txep_bitmap;
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unsigned rxep_shift:5;
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u32 rxep_mask;
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u32 rxep_bitmap;
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/* bit positions for phy_utmi */
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unsigned otg_disable:5;
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/* bit positions for mode */
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unsigned iddig:5;
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unsigned iddig_mux:5;
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/* miscellaneous stuff */
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u8 poll_seconds;
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};
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/*
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* register shadow for suspend
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*/
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struct dsps_context {
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u32 control;
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u32 epintr;
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u32 coreintr;
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u32 phy_utmi;
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u32 mode;
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u32 tx_mode;
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u32 rx_mode;
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};
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/**
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* DSPS glue structure.
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*/
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struct dsps_glue {
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struct device *dev;
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struct platform_device *musb; /* child musb pdev */
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const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
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struct timer_list timer; /* otg_workaround timer */
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unsigned long last_timer; /* last timer data for each instance */
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struct dsps_context context;
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};
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static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
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{
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struct device *dev = musb->controller;
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struct dsps_glue *glue = dev_get_drvdata(dev->parent);
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if (timeout == 0)
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timeout = jiffies + msecs_to_jiffies(3);
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/* Never idle if active, or when VBUS timeout is not set as host */
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if (musb->is_active || (musb->a_wait_bcon == 0 &&
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musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
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dev_dbg(musb->controller, "%s active, deleting timer\n",
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usb_otg_state_string(musb->xceiv->state));
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del_timer(&glue->timer);
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glue->last_timer = jiffies;
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return;
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}
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if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE)
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return;
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if (!musb->g.dev.driver)
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return;
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if (time_after(glue->last_timer, timeout) &&
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timer_pending(&glue->timer)) {
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dev_dbg(musb->controller,
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"Longer idle timer already pending, ignoring...\n");
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return;
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}
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glue->last_timer = timeout;
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dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
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usb_otg_state_string(musb->xceiv->state),
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jiffies_to_msecs(timeout - jiffies));
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mod_timer(&glue->timer, timeout);
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}
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/**
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* dsps_musb_enable - enable interrupts
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*/
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static void dsps_musb_enable(struct musb *musb)
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{
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struct device *dev = musb->controller;
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struct platform_device *pdev = to_platform_device(dev->parent);
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struct dsps_glue *glue = platform_get_drvdata(pdev);
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const struct dsps_musb_wrapper *wrp = glue->wrp;
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void __iomem *reg_base = musb->ctrl_base;
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u32 epmask, coremask;
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/* Workaround: setup IRQs through both register sets. */
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epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
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((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
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coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
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dsps_writel(reg_base, wrp->epintr_set, epmask);
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dsps_writel(reg_base, wrp->coreintr_set, coremask);
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/* Force the DRVVBUS IRQ so we can start polling for ID change. */
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dsps_writel(reg_base, wrp->coreintr_set,
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(1 << wrp->drvvbus) << wrp->usb_shift);
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dsps_musb_try_idle(musb, 0);
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}
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/**
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* dsps_musb_disable - disable HDRC and flush interrupts
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*/
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static void dsps_musb_disable(struct musb *musb)
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{
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struct device *dev = musb->controller;
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struct platform_device *pdev = to_platform_device(dev->parent);
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struct dsps_glue *glue = platform_get_drvdata(pdev);
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const struct dsps_musb_wrapper *wrp = glue->wrp;
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void __iomem *reg_base = musb->ctrl_base;
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dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
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dsps_writel(reg_base, wrp->epintr_clear,
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wrp->txep_bitmap | wrp->rxep_bitmap);
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dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
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}
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static void otg_timer(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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void __iomem *mregs = musb->mregs;
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struct device *dev = musb->controller;
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struct dsps_glue *glue = dev_get_drvdata(dev->parent);
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const struct dsps_musb_wrapper *wrp = glue->wrp;
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u8 devctl;
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unsigned long flags;
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int skip_session = 0;
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/*
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* We poll because DSPS IP's won't expose several OTG-critical
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* status change events (from the transceiver) otherwise.
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*/
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devctl = dsps_readb(mregs, MUSB_DEVCTL);
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dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
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usb_otg_state_string(musb->xceiv->state));
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv->state) {
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case OTG_STATE_A_WAIT_BCON:
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dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
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skip_session = 1;
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/* fall */
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case OTG_STATE_A_IDLE:
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case OTG_STATE_B_IDLE:
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if (devctl & MUSB_DEVCTL_BDEVICE) {
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musb->xceiv->state = OTG_STATE_B_IDLE;
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MUSB_DEV_MODE(musb);
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} else {
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musb->xceiv->state = OTG_STATE_A_IDLE;
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MUSB_HST_MODE(musb);
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}
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if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
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dsps_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
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mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
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break;
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case OTG_STATE_A_WAIT_VFALL:
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musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
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dsps_writel(musb->ctrl_base, wrp->coreintr_set,
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MUSB_INTR_VBUSERROR << wrp->usb_shift);
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break;
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default:
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static irqreturn_t dsps_interrupt(int irq, void *hci)
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{
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struct musb *musb = hci;
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void __iomem *reg_base = musb->ctrl_base;
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struct device *dev = musb->controller;
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struct dsps_glue *glue = dev_get_drvdata(dev->parent);
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const struct dsps_musb_wrapper *wrp = glue->wrp;
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unsigned long flags;
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irqreturn_t ret = IRQ_NONE;
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u32 epintr, usbintr;
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spin_lock_irqsave(&musb->lock, flags);
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/* Get endpoint interrupts */
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epintr = dsps_readl(reg_base, wrp->epintr_status);
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musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
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musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
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if (epintr)
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dsps_writel(reg_base, wrp->epintr_status, epintr);
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/* Get usb core interrupts */
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usbintr = dsps_readl(reg_base, wrp->coreintr_status);
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if (!usbintr && !epintr)
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goto out;
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musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
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if (usbintr)
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dsps_writel(reg_base, wrp->coreintr_status, usbintr);
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dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
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usbintr, epintr);
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/*
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* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
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* DSPS IP's missing ID change IRQ. We need an ID change IRQ to
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* switch appropriately between halves of the OTG state machine.
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* Managing DEVCTL.SESSION per Mentor docs requires that we know its
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* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
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* Also, DRVVBUS pulses for SRP (but not at 5V) ...
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*/
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if (is_host_active(musb) && usbintr & MUSB_INTR_BABBLE)
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pr_info("CAUTION: musb: Babble Interrupt Occurred\n");
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if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
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int drvvbus = dsps_readl(reg_base, wrp->status);
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void __iomem *mregs = musb->mregs;
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u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
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int err;
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err = musb->int_usb & MUSB_INTR_VBUSERROR;
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if (err) {
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/*
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* The Mentor core doesn't debounce VBUS as needed
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* to cope with device connect current spikes. This
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* means it's not uncommon for bus-powered devices
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* to get VBUS errors during enumeration.
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*
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* This is a workaround, but newer RTL from Mentor
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* seems to allow a better one: "re"-starting sessions
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* without waiting for VBUS to stop registering in
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* devctl.
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*/
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musb->int_usb &= ~MUSB_INTR_VBUSERROR;
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musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
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mod_timer(&glue->timer,
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jiffies + wrp->poll_seconds * HZ);
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WARNING("VBUS error workaround (delay coming)\n");
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} else if (drvvbus) {
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MUSB_HST_MODE(musb);
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musb->xceiv->otg->default_a = 1;
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musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
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del_timer(&glue->timer);
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} else {
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musb->is_active = 0;
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MUSB_DEV_MODE(musb);
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musb->xceiv->otg->default_a = 0;
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musb->xceiv->state = OTG_STATE_B_IDLE;
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}
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/* NOTE: this must complete power-on within 100 ms. */
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dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
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drvvbus ? "on" : "off",
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usb_otg_state_string(musb->xceiv->state),
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err ? " ERROR" : "",
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devctl);
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ret = IRQ_HANDLED;
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}
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if (musb->int_tx || musb->int_rx || musb->int_usb)
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ret |= musb_interrupt(musb);
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/* Poll for ID change in OTG port mode */
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if (musb->xceiv->state == OTG_STATE_B_IDLE &&
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musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
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mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
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out:
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spin_unlock_irqrestore(&musb->lock, flags);
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return ret;
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}
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static int dsps_musb_init(struct musb *musb)
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{
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struct device *dev = musb->controller;
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struct dsps_glue *glue = dev_get_drvdata(dev->parent);
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struct platform_device *parent = to_platform_device(dev->parent);
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const struct dsps_musb_wrapper *wrp = glue->wrp;
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void __iomem *reg_base;
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struct resource *r;
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u32 rev, val;
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r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
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if (!r)
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return -EINVAL;
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reg_base = devm_ioremap_resource(dev, r);
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if (IS_ERR(reg_base))
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return PTR_ERR(reg_base);
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musb->ctrl_base = reg_base;
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/* NOP driver needs change if supporting dual instance */
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musb->xceiv = devm_usb_get_phy_by_phandle(dev, "phys", 0);
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if (IS_ERR(musb->xceiv))
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return PTR_ERR(musb->xceiv);
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/* Returns zero if e.g. not clocked */
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rev = dsps_readl(reg_base, wrp->revision);
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if (!rev)
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return -ENODEV;
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usb_phy_init(musb->xceiv);
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setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
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/* Reset the musb */
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dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
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musb->isr = dsps_interrupt;
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/* reset the otgdisable bit, needed for host mode to work */
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val = dsps_readl(reg_base, wrp->phy_utmi);
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val &= ~(1 << wrp->otg_disable);
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dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
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return 0;
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}
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static int dsps_musb_exit(struct musb *musb)
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{
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struct device *dev = musb->controller;
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struct dsps_glue *glue = dev_get_drvdata(dev->parent);
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del_timer_sync(&glue->timer);
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usb_phy_shutdown(musb->xceiv);
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return 0;
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}
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static int dsps_musb_set_mode(struct musb *musb, u8 mode)
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{
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struct device *dev = musb->controller;
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struct dsps_glue *glue = dev_get_drvdata(dev->parent);
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const struct dsps_musb_wrapper *wrp = glue->wrp;
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void __iomem *ctrl_base = musb->ctrl_base;
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void __iomem *base = musb->mregs;
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u32 reg;
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reg = dsps_readl(base, wrp->mode);
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switch (mode) {
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case MUSB_HOST:
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reg &= ~(1 << wrp->iddig);
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/*
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* if we're setting mode to host-only or device-only, we're
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* going to ignore whatever the PHY sends us and just force
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* ID pin status by SW
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*/
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reg |= (1 << wrp->iddig_mux);
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dsps_writel(base, wrp->mode, reg);
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dsps_writel(ctrl_base, wrp->phy_utmi, 0x02);
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break;
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case MUSB_PERIPHERAL:
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reg |= (1 << wrp->iddig);
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/*
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* if we're setting mode to host-only or device-only, we're
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* going to ignore whatever the PHY sends us and just force
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* ID pin status by SW
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*/
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reg |= (1 << wrp->iddig_mux);
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dsps_writel(base, wrp->mode, reg);
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break;
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case MUSB_OTG:
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dsps_writel(base, wrp->phy_utmi, 0x02);
|
|
break;
|
|
default:
|
|
dev_err(glue->dev, "unsupported mode %d\n", mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct musb_platform_ops dsps_ops = {
|
|
.init = dsps_musb_init,
|
|
.exit = dsps_musb_exit,
|
|
|
|
.enable = dsps_musb_enable,
|
|
.disable = dsps_musb_disable,
|
|
|
|
.try_idle = dsps_musb_try_idle,
|
|
.set_mode = dsps_musb_set_mode,
|
|
};
|
|
|
|
static u64 musb_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static int get_int_prop(struct device_node *dn, const char *s)
|
|
{
|
|
int ret;
|
|
u32 val;
|
|
|
|
ret = of_property_read_u32(dn, s, &val);
|
|
if (ret)
|
|
return 0;
|
|
return val;
|
|
}
|
|
|
|
static int get_musb_port_mode(struct device *dev)
|
|
{
|
|
enum usb_dr_mode mode;
|
|
|
|
mode = of_usb_get_dr_mode(dev->of_node);
|
|
switch (mode) {
|
|
case USB_DR_MODE_HOST:
|
|
return MUSB_PORT_MODE_HOST;
|
|
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
return MUSB_PORT_MODE_GADGET;
|
|
|
|
case USB_DR_MODE_UNKNOWN:
|
|
case USB_DR_MODE_OTG:
|
|
default:
|
|
return MUSB_PORT_MODE_DUAL_ROLE;
|
|
}
|
|
}
|
|
|
|
static int dsps_create_musb_pdev(struct dsps_glue *glue,
|
|
struct platform_device *parent)
|
|
{
|
|
struct musb_hdrc_platform_data pdata;
|
|
struct resource resources[2];
|
|
struct resource *res;
|
|
struct device *dev = &parent->dev;
|
|
struct musb_hdrc_config *config;
|
|
struct platform_device *musb;
|
|
struct device_node *dn = parent->dev.of_node;
|
|
int ret;
|
|
|
|
memset(resources, 0, sizeof(resources));
|
|
res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
|
|
if (!res) {
|
|
dev_err(dev, "failed to get memory.\n");
|
|
return -EINVAL;
|
|
}
|
|
resources[0] = *res;
|
|
|
|
res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc");
|
|
if (!res) {
|
|
dev_err(dev, "failed to get irq.\n");
|
|
return -EINVAL;
|
|
}
|
|
resources[1] = *res;
|
|
|
|
/* allocate the child platform device */
|
|
musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
|
|
if (!musb) {
|
|
dev_err(dev, "failed to allocate musb device\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
musb->dev.parent = dev;
|
|
musb->dev.dma_mask = &musb_dmamask;
|
|
musb->dev.coherent_dma_mask = musb_dmamask;
|
|
musb->dev.of_node = of_node_get(dn);
|
|
|
|
glue->musb = musb;
|
|
|
|
ret = platform_device_add_resources(musb, resources,
|
|
ARRAY_SIZE(resources));
|
|
if (ret) {
|
|
dev_err(dev, "failed to add resources\n");
|
|
goto err;
|
|
}
|
|
|
|
config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
|
|
if (!config) {
|
|
dev_err(dev, "failed to allocate musb hdrc config\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
pdata.config = config;
|
|
pdata.platform_ops = &dsps_ops;
|
|
|
|
config->num_eps = get_int_prop(dn, "mentor,num-eps");
|
|
config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
|
|
config->host_port_deassert_reset_at_resume = 1;
|
|
pdata.mode = get_musb_port_mode(dev);
|
|
/* DT keeps this entry in mA, musb expects it as per USB spec */
|
|
pdata.power = get_int_prop(dn, "mentor,power") / 2;
|
|
config->multipoint = of_property_read_bool(dn, "mentor,multipoint");
|
|
|
|
ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
|
|
if (ret) {
|
|
dev_err(dev, "failed to add platform_data\n");
|
|
goto err;
|
|
}
|
|
|
|
ret = platform_device_add(musb);
|
|
if (ret) {
|
|
dev_err(dev, "failed to register musb device\n");
|
|
goto err;
|
|
}
|
|
return 0;
|
|
|
|
err:
|
|
platform_device_put(musb);
|
|
return ret;
|
|
}
|
|
|
|
static int dsps_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
const struct dsps_musb_wrapper *wrp;
|
|
struct dsps_glue *glue;
|
|
int ret;
|
|
|
|
if (!strcmp(pdev->name, "musb-hdrc"))
|
|
return -ENODEV;
|
|
|
|
match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
|
|
if (!match) {
|
|
dev_err(&pdev->dev, "fail to get matching of_match struct\n");
|
|
return -EINVAL;
|
|
}
|
|
wrp = match->data;
|
|
|
|
/* allocate glue */
|
|
glue = kzalloc(sizeof(*glue), GFP_KERNEL);
|
|
if (!glue) {
|
|
dev_err(&pdev->dev, "unable to allocate glue memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
glue->dev = &pdev->dev;
|
|
glue->wrp = wrp;
|
|
|
|
platform_set_drvdata(pdev, glue);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "pm_runtime_get_sync FAILED");
|
|
goto err2;
|
|
}
|
|
|
|
ret = dsps_create_musb_pdev(glue, pdev);
|
|
if (ret)
|
|
goto err3;
|
|
|
|
return 0;
|
|
|
|
err3:
|
|
pm_runtime_put(&pdev->dev);
|
|
err2:
|
|
pm_runtime_disable(&pdev->dev);
|
|
kfree(glue);
|
|
return ret;
|
|
}
|
|
|
|
static int dsps_remove(struct platform_device *pdev)
|
|
{
|
|
struct dsps_glue *glue = platform_get_drvdata(pdev);
|
|
|
|
platform_device_unregister(glue->musb);
|
|
|
|
/* disable usbss clocks */
|
|
pm_runtime_put(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
kfree(glue);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dsps_musb_wrapper am33xx_driver_data = {
|
|
.revision = 0x00,
|
|
.control = 0x14,
|
|
.status = 0x18,
|
|
.epintr_set = 0x38,
|
|
.epintr_clear = 0x40,
|
|
.epintr_status = 0x30,
|
|
.coreintr_set = 0x3c,
|
|
.coreintr_clear = 0x44,
|
|
.coreintr_status = 0x34,
|
|
.phy_utmi = 0xe0,
|
|
.mode = 0xe8,
|
|
.tx_mode = 0x70,
|
|
.rx_mode = 0x74,
|
|
.reset = 0,
|
|
.otg_disable = 21,
|
|
.iddig = 8,
|
|
.iddig_mux = 7,
|
|
.usb_shift = 0,
|
|
.usb_mask = 0x1ff,
|
|
.usb_bitmap = (0x1ff << 0),
|
|
.drvvbus = 8,
|
|
.txep_shift = 0,
|
|
.txep_mask = 0xffff,
|
|
.txep_bitmap = (0xffff << 0),
|
|
.rxep_shift = 16,
|
|
.rxep_mask = 0xfffe,
|
|
.rxep_bitmap = (0xfffe << 16),
|
|
.poll_seconds = 2,
|
|
};
|
|
|
|
static const struct of_device_id musb_dsps_of_match[] = {
|
|
{ .compatible = "ti,musb-am33xx",
|
|
.data = (void *) &am33xx_driver_data, },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
|
|
|
|
#ifdef CONFIG_PM
|
|
static int dsps_suspend(struct device *dev)
|
|
{
|
|
struct dsps_glue *glue = dev_get_drvdata(dev);
|
|
const struct dsps_musb_wrapper *wrp = glue->wrp;
|
|
struct musb *musb = platform_get_drvdata(glue->musb);
|
|
void __iomem *mbase = musb->ctrl_base;
|
|
|
|
glue->context.control = dsps_readl(mbase, wrp->control);
|
|
glue->context.epintr = dsps_readl(mbase, wrp->epintr_set);
|
|
glue->context.coreintr = dsps_readl(mbase, wrp->coreintr_set);
|
|
glue->context.phy_utmi = dsps_readl(mbase, wrp->phy_utmi);
|
|
glue->context.mode = dsps_readl(mbase, wrp->mode);
|
|
glue->context.tx_mode = dsps_readl(mbase, wrp->tx_mode);
|
|
glue->context.rx_mode = dsps_readl(mbase, wrp->rx_mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dsps_resume(struct device *dev)
|
|
{
|
|
struct dsps_glue *glue = dev_get_drvdata(dev);
|
|
const struct dsps_musb_wrapper *wrp = glue->wrp;
|
|
struct musb *musb = platform_get_drvdata(glue->musb);
|
|
void __iomem *mbase = musb->ctrl_base;
|
|
|
|
dsps_writel(mbase, wrp->control, glue->context.control);
|
|
dsps_writel(mbase, wrp->epintr_set, glue->context.epintr);
|
|
dsps_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
|
|
dsps_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
|
|
dsps_writel(mbase, wrp->mode, glue->context.mode);
|
|
dsps_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
|
|
dsps_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
|
|
|
|
static struct platform_driver dsps_usbss_driver = {
|
|
.probe = dsps_probe,
|
|
.remove = dsps_remove,
|
|
.driver = {
|
|
.name = "musb-dsps",
|
|
.pm = &dsps_pm_ops,
|
|
.of_match_table = musb_dsps_of_match,
|
|
},
|
|
};
|
|
|
|
MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
|
|
MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
|
|
MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
module_platform_driver(dsps_usbss_driver);
|