1a4baafa7d
The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
328 lines
8.9 KiB
ArmAsm
328 lines
8.9 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-arm6,7.S
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*
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* Copyright (C) 1997-2000 Russell King
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the ARM610 & ARM710.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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ENTRY(cpu_arm6_dcache_clean_area)
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ENTRY(cpu_arm7_dcache_clean_area)
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mov pc, lr
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/*
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* Function: arm6_7_data_abort ()
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*
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* Params : r2 = pt_regs
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* : r4 = aborted context pc
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* : r5 = aborted context psr
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*
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* Purpose : obtain information about current aborted instruction
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*
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* Returns : r4-r5, r10-r11, r13 preserved
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*/
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ENTRY(cpu_arm7_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r4] @ read arm instruction
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tst r8, #1 << 20 @ L = 0 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #15 << 24
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add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
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nop
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/* 0 */ b .data_unknown
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/* 1 */ b do_DataAbort @ swp
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/* 2 */ b .data_unknown
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/* 3 */ b .data_unknown
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/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
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/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
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/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
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/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
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/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
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/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
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/* a */ b .data_unknown
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/* b */ b .data_unknown
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/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
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/* d */ b do_DataAbort @ ldc rd, [rn, #m]
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/* e */ b .data_unknown
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/* f */
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.data_unknown: @ Part of jumptable
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mov r0, r4
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mov r1, r8
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b baddataabort
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ENTRY(cpu_arm6_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r4] @ read arm instruction
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tst r8, #1 << 20 @ L = 0 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #14 << 24
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teq r7, #8 << 24 @ was it ldm/stm
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bne do_DataAbort
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.data_arm_ldmstm:
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tst r8, #1 << 21 @ check writeback bit
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beq do_DataAbort @ no writeback -> no fixup
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mov r7, #0x11
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orr r7, r7, #0x1100
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and r6, r8, r7
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and r9, r8, r7, lsl #1
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add r6, r6, r9, lsr #1
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and r9, r8, r7, lsl #2
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add r6, r6, r9, lsr #2
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and r9, r8, r7, lsl #3
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add r6, r6, r9, lsr #3
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add r6, r6, r6, lsr #8
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add r6, r6, r6, lsr #4
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and r6, r6, #15 @ r6 = no. of registers to transfer.
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsl #2 @ Undo increment
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addeq r7, r7, r6, lsl #2 @ Undo decrement
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_apply_r6_and_rn:
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6 @ Undo incrmenet
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addeq r7, r7, r6 @ Undo decrement
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrpreconst:
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tst r8, #1 << 21 @ check writeback bit
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beq do_DataAbort @ no writeback -> no fixup
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.data_arm_lateldrpostconst:
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movs r6, r8, lsl #20 @ Get offset
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beq do_DataAbort @ zero -> no fixup
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and r9, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsr #20 @ Undo increment
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addeq r7, r7, r6, lsr #20 @ Undo decrement
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str r7, [r2, r9, lsr #14] @ Put register 'Rn'
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b do_DataAbort
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.data_arm_lateldrprereg:
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tst r8, #1 << 21 @ check writeback bit
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beq do_DataAbort @ no writeback -> no fixup
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.data_arm_lateldrpostreg:
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and r7, r8, #15 @ Extract 'm' from instruction
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ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
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mov r9, r8, lsr #7 @ get shift count
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ands r9, r9, #31
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and r7, r8, #0x70 @ get shift type
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orreq r7, r7, #8 @ shift count = 0
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add pc, pc, r7
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nop
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mov r6, r6, lsl r9 @ 0: LSL #!0
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b .data_arm_apply_r6_and_rn
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b .data_arm_apply_r6_and_rn @ 1: LSL #0
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nop
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b .data_unknown @ 2: MUL?
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nop
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b .data_unknown @ 3: MUL?
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nop
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mov r6, r6, lsr r9 @ 4: LSR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, lsr #32 @ 5: LSR #32
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ 6: MUL?
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nop
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b .data_unknown @ 7: MUL?
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nop
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mov r6, r6, asr r9 @ 8: ASR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, asr #32 @ 9: ASR #32
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ A: MUL?
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nop
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b .data_unknown @ B: MUL?
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nop
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mov r6, r6, ror r9 @ C: ROR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, rrx @ D: RRX
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ E: MUL?
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nop
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b .data_unknown @ F: MUL?
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/*
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* Function: arm6_7_proc_init (void)
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* : arm6_7_proc_fin (void)
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*
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* Notes : This processor does not require these
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*/
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ENTRY(cpu_arm6_proc_init)
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ENTRY(cpu_arm7_proc_init)
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mov pc, lr
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ENTRY(cpu_arm6_proc_fin)
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ENTRY(cpu_arm7_proc_fin)
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mov r0, #0x31 @ ....S..DP...M
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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ENTRY(cpu_arm6_do_idle)
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ENTRY(cpu_arm7_do_idle)
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mov pc, lr
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/*
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* Function: arm6_7_switch_mm(unsigned long pgd_phys)
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* Params : pgd_phys Physical address of page table
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* Purpose : Perform a task switch, saving the old processes state, and restoring
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* the new.
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*/
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ENTRY(cpu_arm6_switch_mm)
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ENTRY(cpu_arm7_switch_mm)
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#ifdef CONFIG_MMU
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ flush cache
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mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
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mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
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#endif
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mov pc, lr
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/*
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* Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
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* Params : r0 = Address to set
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* : r1 = value to set
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* Purpose : Set a PTE and flush it out of any WB cache
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*/
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.align 5
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ENTRY(cpu_arm6_set_pte_ext)
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ENTRY(cpu_arm7_set_pte_ext)
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#ifdef CONFIG_MMU
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armv3_set_pte_ext wc_disable=0
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#endif /* CONFIG_MMU */
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mov pc, lr
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/*
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* Function: _arm6_7_reset
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_arm6_reset)
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ENTRY(cpu_arm7_reset)
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ flush cache
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#ifdef CONFIG_MMU
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mcr p15, 0, r1, c5, c0, 0 @ flush TLB
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#endif
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mov r1, #0x30
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mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
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mov pc, r0
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ENDPROC(cpu_arm6_reset)
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ENDPROC(cpu_arm7_reset)
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.popsection
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__CPUINIT
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.type __arm6_setup, #function
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__arm6_setup: mov r0, #0
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mcr p15, 0, r0, c7, c0 @ flush caches on v3
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
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mov r0, #0x3d @ . ..RS BLDP WCAM
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orr r0, r0, #0x100 @ . ..01 0011 1101
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#else
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mov r0, #0x3c @ . ..RS BLDP WCA.
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#endif
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mov pc, lr
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.size __arm6_setup, . - __arm6_setup
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.type __arm7_setup, #function
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__arm7_setup: mov r0, #0
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mcr p15, 0, r0, c7, c0 @ flush caches on v3
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
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mcr p15, 0, r0, c3, c0 @ load domain access register
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mov r0, #0x7d @ . ..RS BLDP WCAM
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orr r0, r0, #0x100 @ . ..01 0111 1101
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#else
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mov r0, #0x7c @ . ..RS BLDP WCA.
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#endif
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mov pc, lr
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.size __arm7_setup, . - __arm7_setup
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
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define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
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define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
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.section ".rodata"
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string cpu_arch_name, "armv3"
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string cpu_elf_name, "v3"
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string cpu_arm6_name, "ARM6"
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string cpu_arm610_name, "ARM610"
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string cpu_arm7_name, "ARM7"
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string cpu_arm710_name, "ARM710"
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
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cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
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.type __\name\()_proc_info, #object
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__\name\()_proc_info:
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.long \cpu_val
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.long \cpu_mask
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.long \cpu_mm_mmu_flags
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b \cpu_flush
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_26BIT
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.long \cpu_name
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.long \cpu_proc_funcs
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.long v3_tlb_fns
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.long v3_user_fns
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.long v3_cache_fns
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.size __\name\()_proc_info, . - __\name\()_proc_info
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.endm
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arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \
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0x00000c1e, __arm6_setup, arm6_processor_functions
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arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
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0x00000c1e, __arm6_setup, arm6_processor_functions
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arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \
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0x00000c1e, __arm7_setup, arm7_processor_functions
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arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
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PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ, \
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__arm7_setup, arm7_processor_functions
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