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alistair23-linux/arch/arm64/boot/dts/freescale/imx8mp.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/reset/imx8mp-mediamix.h>
#include <dt-bindings/reset/imx-hdmimix-reset.h>
#include "imx8mp-pinfunc.h"
/ {
compatible = "fsl,imx8mp";
interrupt-parent = <&gpc>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
isi0 = &isi_0;
isi1 = &isi_1;
csi0 = &mipi_csi_0;
csi1 = &mipi_csi_1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>; /* two CLK32 periods */
next-level-cache = <&A53_L2>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
enable-method = "psci";
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>; /* two CLK32 periods */
next-level-cache = <&A53_L2>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>; /* two CLK32 periods */
next-level-cache = <&A53_L2>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>; /* two CLK32 periods */
next-level-cache = <&A53_L2>;
clocks = <&clk IMX8MP_CLK_ARM>;
operating-points-v2 = <&a53_opp_table>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {
compatible = "cache";
};
};
a53_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <850000>;
opp-supported-hw = <0x8a0>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <950000>;
opp-supported-hw = <0xa0>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1000000>;
opp-supported-hw = <0x20>, <0x3>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
ddr_pmu0: ddr_pmu@3d800000 {
compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x0 0x3d800000 0x0 0x400000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
edacmc: memory-controller@3d400000 {
compatible = "fsl,imx8mp-ddrc";
reg = <0x0 0x3d400000 0x0 0x400000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
resmem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ocram: ocram@900000 {
no-map;
reg = <0 0x900000 0 0x60000>;
};
ocram_e: ocram_e@980000 {
no-map;
reg = <0 0x980000 0 0x10000>;
};
/*
* Memory reserved for optee usage. Please do not use.
* This will be automaticky added to dtb if OP-TEE is installed.
* optee@56000000 {
* reg = <0 0x56000000 0 0x2000000>;
* no-map;
* };
*/
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
alloc-ranges = <0 0x40000000 0 0xC0000000>;
linux,cma-default;
};
dsp_reserved: dsp@92400000 {
no-map;
reg = <0 0x92400000 0 0x2000000>;
};
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
};
osc_24m: clock-osc-24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc_24m";
};
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext1";
};
clk_ext2: clock-ext2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext2";
};
clk_ext3: clock-ext3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext3";
};
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-output-names = "clk_ext4";
};
busfreq { /* BUSFREQ */
compatible = "fsl,imx_busfreq";
clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>,
<&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>,
<&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>,
<&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>,
<&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>,
<&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_DRAM_PLL>;
clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
"dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
"sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
"sys_pll1_800m", "dram_pll_div";
};
power-domains {
compatible = "simple-bus";
/* HSIO SS */
hsiomix_pd: hsiomix-pd {
compatible = "fsl,imx8m-pm-domain";
active-wakeup;
rpm-always-on;
#power-domain-cells = <0>;
domain-index = <0>;
domain-name = "hsiomix";
};
pcie_pd: pcie-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <1>;
domain-name = "pcie";
parent-domains = <&hsiomix_pd>;
};
usb_otg1_pd: usbotg1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <2>;
domain-name = "usb_otg1";
parent-domains = <&hsiomix_pd>;
};
usb_otg2_pd: usbotg2-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <3>;
domain-name = "usb_otg2";
parent-domains = <&hsiomix_pd>;
};
/* MLMIX */
mlmix_pd: mlmix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <4>;
domain-name = "mlmix";
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
};
audiomix_pd: audiomix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <5>;
domain-name = "audiomix";
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_AUDIO_AXI_DIV>;
};
gpumix_pd: gpumix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <6>;
domain-name = "gpumix";
clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>,
<&clk IMX8MP_CLK_GPU_AXI>;
};
gpu2d_pd: gpu2d-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <7>;
domain-name = "gpu2d";
parent-domains = <&gpumix_pd>;
clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
};
gpu3d_pd: gpu3d-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <8>;
domain-name = "gpu3d";
parent-domains = <&gpumix_pd>;
clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
<&clk IMX8MP_CLK_GPU3D_SHADER_DIV>;
};
vpumix_pd: vpumix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <9>;
domain-name = "vpumix";
clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
};
vpu_g1_pd: vpug1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <10>;
domain-name = "vpu_g1";
parent-domains = <&vpumix_pd>;
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
};
vpu_g2_pd: vpug2-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <11>;
domain-name = "vpu_g2";
parent-domains = <&vpumix_pd>;
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
};
vpu_h1_pd: vpuh1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <12>;
domain-name = "vpu_h1";
parent-domains = <&vpumix_pd>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
mediamix_pd: mediamix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <13>;
domain-name = "mediamix";
clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
ispdwp_pd: power-domain@14 {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <14>;
domain-name = "ispdwp";
parent-domains = <&mediamix_pd>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
};
mipi_phy1_pd: mipiphy1-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <15>;
domain-name = "mipi_phy1";
parent-domains = <&mediamix_pd>;
};
mipi_phy2_pd: mipiphy2-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <16>;
domain-name = "mipi_phy2";
parent-domains = <&mediamix_pd>;
};
hdmimix_pd: hdmimix-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <17>;
domain-name = "hdmimix";
clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_REF_266M>;
};
hdmi_phy_pd: hdmiphy-pd {
compatible = "fsl,imx8m-pm-domain";
#power-domain-cells = <0>;
domain-index = <18>;
domain-name = "hdmi_phy";
parent-domains = <&hdmimix_pd>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 0x0>;
trips {
cpu_alert0: trip0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 0x1>;
trips {
soc_alert0: trip0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit0: trip1 {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
caam_sm: caam-sm@100000 {
compatible = "fsl,imx6q-caam-sm";
reg = <0x100000 0x8000>;
};
aips1: bus@30000000 {
compatible = "simple-bus";
reg = <0x30000000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@30200000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@30210000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30210000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@30220000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30220000 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@30230000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30230000 0x10000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@30240000 {
compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
reg = <0x30240000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
tmu: tmu@30260000 {
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
#thermal-sensor-cells = <1>;
};
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
status = "disabled";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mp-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mp-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
ocotp: ocotp-ctrl@30350000 {
compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
/* For nvmem subnodes */
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
eth_mac1: mac-address@640 {
reg = <0x90 6>;
};
eth_mac2: mac-address@650 {
reg = <0x96 6>;
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
"syscon";
reg = <0x30360000 0x10000>;
};
irq_sec_vio: caam_secvio {
compatible = "fsl,imx6q-caam-secvio";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
jtag-tamper = "disabled";
watchdog-tamper = "enabled";
internal-boot-tamper = "enabled";
external-pin-tamper = "disabled";
};
caam_snvs: caam-snvs@30370000 {
compatible = "fsl,imx6q-caam-snvs";
reg = <0x30370000 0x10000>;
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
clock-names = "ipg";
};
snvs: snvs@30370000 {
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x30370000 0x10000>;
snvs_rtc: snvs-rtc-lp{
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap =<&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
clock-names = "snvs-rtc";
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
clock-names = "snvs";
linux,keycode = <KEY_POWER>;
wakeup-source;
};
};
clk: clock-controller@30380000 {
compatible = "fsl,imx8mp-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
<&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <1000000000>,
<800000000>,
<500000000>,
<400000000>,
<800000000>,
<400000000>,
<393216000>,
<361267200>,
<2079000000>;
};
src: src@30390000 {
compatible = "fsl,imx8mp-src", "fsl,imx8mq-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
gpc: gpc@303a0000 {
compatible = "fsl,imx8mp-gpc";
reg = <0x303a0000 0x10000>;
interrupt-parent = <&gic>;
interrupt-controller;
broken-wake-request-signals;
#interrupt-cells = <3>;
};
};
aips2: bus@30400000 {
compatible = "simple-bus";
reg = <0x30400000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pwm1: pwm@30660000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
<&clk IMX8MP_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@30670000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30670000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
<&clk IMX8MP_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@30680000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30680000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
<&clk IMX8MP_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@30690000 {
compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
reg = <0x30690000 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
<&clk IMX8MP_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
system_counter: timer@306a0000 {
compatible = "nxp,sysctr-timer";
reg = <0x306a0000 0x20000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>;
clock-names = "per";
};
};
aips3: bus@30800000 {
compatible = "simple-bus";
reg = <0x30800000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
<&clk IMX8MP_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
<&clk IMX8MP_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
<&clk IMX8MP_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
status = "disabled";
};
flexcan1: can@308c0000 {
compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN1_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source= <0>;
fsl,stop-mode = <&gpr 0x10 4 0x10 20>;
status = "disabled";
};
flexcan2: can@308d0000 {
compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
reg = <0x308d0000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN2_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source= <0>;
fsl,stop-mode = <&gpr 0x10 5 0x10 21>;
status = "disabled";
};
crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30900000 0x40000>;
ranges = <0 0x30900000 0x40000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_AHB>,
<&clk IMX8MP_CLK_IPG_ROOT>;
clock-names = "aclk", "ipg";
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
};
};
i2c1: i2c@30a20000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
status = "disabled";
};
i2c2: i2c@30a30000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
reg = <0x30a30000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
status = "disabled";
};
i2c3: i2c@30a40000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
reg = <0x30a40000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
status = "disabled";
};
i2c4: i2c@30a50000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
reg = <0x30a50000 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
status = "disabled";
};
uart4: serial@30a60000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30a60000 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
<&clk IMX8MP_CLK_UART4_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
mu: mu@30aa0000 {
compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
reg = <0x30aa0000 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MU_ROOT>;
clock-names = "mu";
#mbox-cells = <2>;
};
i2c5: i2c@30ad0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
reg = <0x30ad0000 0x10000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
status = "disabled";
};
i2c6: i2c@30ae0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
reg = <0x30ae0000 0x10000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
status = "disabled";
};
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_NAND_USDHC_BUS>,
<&clk IMX8MP_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
flexspi: spi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8mm-fspi";
reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
<&clk IMX8MP_CLK_QSPI_ROOT>;
clock-names = "fspi", "fspi_en";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
status = "disabled";
};
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
<&clk IMX8MP_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
fec: ethernet@30be0000 {
compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
<&clk IMX8MP_CLK_SIM_ENET_ROOT>,
<&clk IMX8MP_CLK_ENET_TIMER>,
<&clk IMX8MP_CLK_ENET_REF>,
<&clk IMX8MP_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_TIMER>,
<&clk IMX8MP_CLK_ENET_REF>,
<&clk IMX8MP_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
nvmem-cells = <&eth_mac1>;
nvmem-cell-names = "mac-address";
nvmem_macaddr_swap;
stop-mode = <&gpr 0x10 3>;
fsl,wakeup_irq = <2>;
status = "disabled";
};
eqos: ethernet@30bf0000 {
compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x30bf0000 0x10000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eth_wake_irq", "macirq";
clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
<&clk IMX8MP_CLK_ENET_QOS>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
<&clk IMX8MP_CLK_ENET_QOS>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <100000000>, <125000000>;
nvmem-cells = <&eth_mac2>;
nvmem-cell-names = "mac-address";
nvmem_macaddr_swap;
intf_mode = <&gpr 0x4>;
status = "disabled";
};
};
aips5: bus@30c00000 {
compatible = "simple-bus";
reg = <0x30c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
spba-bus@30c00000 {
compatible = "fsl,spba-bus", "simple-bus";
reg = <0x30c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sai1: sai@30c10000 {
compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai";
reg = <0x30c10000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
dma-names = "rx", "tx";
fsl,shared-interrupt;
fsl,dataline = <0 0xff 0xff>;
power-domains = <&audiomix_pd>;
status = "disabled";
};
sai2: sai@30c20000 {
compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai";
reg = <0x30c20000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
dma-names = "rx", "tx";
fsl,shared-interrupt;
fsl,dataline = <0 0xf 0xf>;
power-domains = <&audiomix_pd>;
status = "disabled";
};
sai3: sai@30c30000 {
compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai";
reg = <0x30c30000 0x10000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
dma-names = "rx", "tx";
fsl,shared-interrupt;
fsl,dataline = <0 0x3 0x3>;
power-domains = <&audiomix_pd>;
status = "disabled";
};
sai5: sai@30c50000 {
compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai";
reg = <0x30c50000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
dma-names = "rx", "tx";
fsl,shared-interrupt;
fsl,dataline = <0 0xf 0xf>;
power-domains = <&audiomix_pd>;
status = "disabled";
};
sai6: sai@30c60000 {
compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai";
reg = <0x30c60000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
<&clk IMX8MP_CLK_DUMMY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
<&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
dma-names = "rx", "tx";
fsl,shared-interrupt;
power-domains = <&audiomix_pd>;
status = "disabled";
};
sai7: sai@30c80000 {
compatible = "fsl,imx8mq-sai", "fsl,imx6sx-sai";
reg = <0x30c80000 0x10000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
dma-names = "rx", "tx";
fsl,shared-interrupt;
power-domains = <&audiomix_pd>;
status = "disabled";
};
easrc: easrc@30c90000 {
compatible = "fsl,imx8mn-easrc";
reg = <0x30c90000 0x10000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
clock-names = "mem";
dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
<&sdma2 18 23 0> , <&sdma2 19 23 0>,
<&sdma2 20 23 0> , <&sdma2 21 23 0>,
<&sdma2 22 23 0> , <&sdma2 23 23 0>;
dma-names = "ctx0_rx", "ctx0_tx",
"ctx1_rx", "ctx1_tx",
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-width = <16>;
power-domains = <&audiomix_pd>;
status = "disabled";
};
micfil: micfil@30ca0000 {
compatible = "fsl,imx8mp-micfil";
reg = <0x30ca0000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_PDM_ROOT>,
<&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>,
<&clk IMX8MP_CLK_EXT3>;
clock-names = "ipg_clk", "ipg_clk_app",
"pll8k", "pll11k", "clkext3";
dmas = <&sdma2 24 25 0x80000000>;
dma-names = "rx";
power-domains = <&audiomix_pd>;
status = "disabled";
};
aud2htx: aud2htx@30cb0000 {
compatible = "fsl,imx8mp-aud2htx";
reg = <0x30cb0000 0x10000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>;
clock-names = "bus";
dmas = <&sdma2 26 2 0>;
dma-names = "tx";
power-domains = <&audiomix_pd>;
status = "disabled";
};
xcvr: xcvr@30cc0000 {
compatible = "fsl,imx8mp-xcvr";
reg = <0x30cc0000 0x800>,
<0x30cc0800 0x400>,
<0x30cc0c00 0x080>,
<0x30cc0e00 0x080>;
reg-names = "ram", "regs", "rxfifo",
"txfifo";
interrupts = /* XCVR IRQ 0 */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
/* XCVR IRQ 1 */
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
/* XCVR PHY - SPDIF wakeup IRQ */
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
clock-names = "ipg", "phy", "spba", "pll_ipg";
dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
dma-names = "rx", "tx";
fsl,xcvr-fw = "imx/xcvr/xcvr-imx8mp.bin";
resets = <&audiomix_reset 0>;
power-domains = <&audiomix_pd>;
status = "disabled";
};
};
sdma3: dma-controller@30e00000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma";
reg = <0x30e00000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
fsl,ratio-1-1;
power-domains = <&audiomix_pd>;
status = "disabled";
};
sdma2: dma-controller@30e10000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx7d-sdma";
reg = <0x30e10000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MP_CLK_AUDIO_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
fsl,ratio-1-1;
power-domains = <&audiomix_pd>;
status = "disabled";
};
audiomix: audiomix@30e20000 {
compatible = "fsl,imx8mp-audiomix";
reg = <0x30e20000 0x10000>;
audiomix_clk: clock-controller {
compatible = "fsl,imx8mp-audiomix-clk";
#clock-cells = <1>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "audio_root";
power-domains = <&audiomix_pd>;
};
audiomix_reset: reset-controller {
compatible = "fsl,imx8mp-audiomix-reset";
power-domains = <&audiomix_pd>;
#reset-cells = <1>;
};
audiomix_dsp: audiomix_dsp {
compatible = "fsl,audiomix-dsp";
};
};
mu2: mu2@30e60000 {
compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu";
reg = <0x30E60000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
fsl,dsp_ap_mu_id = <2>;
#mbox-cells = <2>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>;
status = "okay";
};
};
aips4: bus@32c00000 {
compatible = "simple-bus";
reg = <0x32c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mipi_dsi: mipi_dsi@32e60000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x10000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
clock-names = "cfg", "pll-ref";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
assigned-clock-rates = <27000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mipi_phy1_pd>;
status = "disabled";
port@0 {
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
lcdif1: lcd-controller@32e80000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-lcdif1";
reg = <0x32e80000 0x10000>;
clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "pix", "disp-axi", "disp-apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <0>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
blk-ctl = <&mediamix_blk_ctl>;
power-domains = <&mediamix_pd>;
status = "disabled";
lcdif1_disp: port@0 {
reg = <0>;
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
lcdif2: lcd-controller@32e90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-lcdif2";
reg = <0x32e90000 0x10000>;
clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "pix", "disp-axi", "disp-apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <1039500000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mediamix_pd>;
status = "disabled";
lcdif2_disp: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
lcdif2_disp_ldb_ch0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ldb_ch0>;
};
lcdif2_disp_ldb_ch1: endpoint@1 {
reg = <1>;
remote-endpoint = <&ldb_ch1>;
};
};
};
mediamix_blk_ctl: blk-ctl@32ec0000 {
compatible = "fsl,imx8mp-mediamix-blk-ctl",
"syscon";
reg = <0x32ec0000 0x10000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
ldb: ldb@32ec005c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ldb";
clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>;
clock-names = "ldb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
gpr = <&mediamix_blk_ctl>;
power-domains = <&mediamix_pd>;
status = "disabled";
lvds-channel@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phys = <&ldb_phy1>;
phy-names = "ldb_phy";
status = "disabled";
port@0 {
reg = <0>;
ldb_ch0: endpoint {
remote-endpoint = <&lcdif2_disp_ldb_ch0>;
};
};
};
lvds-channel@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phys = <&ldb_phy2>;
phy-names = "ldb_phy";
status = "disabled";
port@0 {
reg = <0>;
ldb_ch1: endpoint {
remote-endpoint = <&lcdif2_disp_ldb_ch1>;
};
};
};
};
/* TODO for HDMI PHY power on */
hdmi_blk: hdmi-blk@32fc0000 {
compatible = "syscon";
reg = <0x32fc0000 0x1000>;
};
hdmimix: hdmimix@32fc0000 {
compatible = "fsl,imx8mp-audiomix", "fsl,imx8mp-hdmimix";
reg = <0x32fc0000 0x1000>;
hdmimix_clk: clock-controller {
compatible = "fsl,imx8mp-hdmimix-clk";
#clock-cells = <1>;
clocks = <&clk IMX8MP_CLK_DUMMY>;
clock-names = "dummy";
status = "disabled";
};
hdmimix_reset: reset-controller {
compatible = "fsl,imx8mp-hdmimix-reset";
#reset-cells = <1>;
status = "disabled";
};
};
irqsteer_hdmi: irqsteer@32fc2000 {
compatible = "fsl,imx-irqsteer";
reg = <0x32fc2000 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
fsl,channel = <1>;
fsl,num-irqs = <64>;
clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_IRQS_STEER_CLK>;
clock-names = "ipg";
assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <200000000>;
resets = <&hdmimix_reset IMX_HDMIMIX_IRQ_STEER_RESET>;
status = "disabled";
};
hdmi_pavi: hdmi-pai-pvi@32fc4000 {
compatible = "fsl,imx8mp-hdmi-pavi";
reg = <0x32fc4000 0x1000>;
clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_GPA_CLK>;
clock-names = "pvi_clk", "pai_clk";
resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PAI_RESET>,
<&hdmimix_reset IMX_HDMIMIX_HDMI_PVI_RESET>;
reset-names = "pai_rst", "pvi_rst";
status = "disabled";
};
lcdif3: lcd-controller@32fc6000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-lcdif3";
reg = <0x32fc6000 0x10000>;
clocks = <&hdmiphy 0>,
<&clk IMX8MP_CLK_HDMI_AXI>,
<&clk IMX8MP_CLK_HDMI_APB>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_APB_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_B_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_TX_PIX_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_APB_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_B_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PDI_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_PIX_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_LCDIF_SPU_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_NOC_HDMI_CLK>;
clock-names = "pix", "disp-axi", "disp-apb",
"mix_apb","mix_axi", "xtl_24m", "mix_pix", "lcdif_apb",
"lcdif_axi", "lcdif_pdi", "lcdif_pix", "lcdif_spu",
"noc_hdmi";
assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
<&clk IMX8MP_CLK_HDMI_APB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <500000000>, <200000000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_hdmi>;
resets = <&hdmimix_reset IMX_HDMIMIX_LCDIF_RESET>;
power-domains = <&hdmimix_pd>;
status = "disabled";
lcdif3_disp: port@0 {
reg = <0>;
lcdif3_to_hdmi: endpoint {
remote-endpoint = <&hdmi_from_lcdif3>;
};
};
};
hdmi: hdmi@32fd8000 {
compatible = "fsl,imx8mp-hdmi";
reg = <0x32fd8000 0x7eff>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&irqsteer_hdmi>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_24M>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PREP_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SKP_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_SFR_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_CEC_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_APB_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_HPI_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PIPE_CLK_SEL>;
clock-names = "iahb", "isfr",
"phy_int", "prep_clk", "skp_clk", "sfr_clk", "pix_clk",
"cec_clk", "apb_clk", "hpi_clk", "fdcc_ref", "pipe_clk";
assigned-clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_AXI>,
<&clk IMX8MP_CLK_HDMI_24M>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <200000000>, <500000000>, <24000000>;
phys = <&hdmiphy>;
phy-names = "hdmi";
resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_TX_RESET>;
gpr = <&hdmi_blk>;
power-domains = <&hdmi_phy_pd>;
status = "disabled";
port@0 {
hdmi_from_lcdif3: endpoint {
remote-endpoint = <&lcdif3_to_hdmi>;
};
};
};
hdmiphy: hdmiphy@32fdff00 {
compatible = "fsl,samsung-hdmi-phy";
reg = <0x32fdff00 0x100>;
#clock-cells = <1>;
clocks = <&hdmimix_clk IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK>,
<&hdmimix_clk IMX8MP_CLK_HDMIMIX_GLOBAL_XTAL24M_CLK>;
clock-names = "apb", "ref";
clock-output-names = "hdmi_phy";
#phy-cells = <0>;
resets = <&hdmimix_reset IMX_HDMIMIX_HDMI_PHY_RESET>;
status = "disabled";
};
mediamix_gasket0: gasket@32ec0060 {
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
reg = <0x32ec0060 0x28>;
};
mediamix_gasket1: gasket@32ec0090 {
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
reg = <0x32ec0090 0x28>;
};
ldb_phy: phy@32ec0128 {
compatible = "fsl,imx8mp-lvds-phy";
#address-cells = <1>;
#size-cells = <0>;
gpr = <&mediamix_blk_ctl>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "apb";
power-domains = <&mediamix_pd>;
status = "disabled";
ldb_phy1: port@0 {
reg = <0>;
#phy-cells = <0>;
};
ldb_phy2: port@1 {
reg = <1>;
#phy-cells = <0>;
};
};
mediamix_gpr: media_gpr@32ec0008 {
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
reg = <0x32ec0008 0x4>;
};
cameradev: camera {
compatible = "fsl,mxc-md", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
isi_0: isi@32e00000 {
compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi";
reg = <0x32e00000 0x2000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interface = <2 0 2>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
assigned-clock-rates = <500000000>, <200000000>;
no-reset-control;
power-domains = <&mediamix_pd>;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
m2m_device{
compatible = "imx-isi-m2m";
status = "disabled";
};
};
isi_1: isi@32e02000 {
compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi";
reg = <0x32e02000 0x2000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interface = <3 0 2>;
clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
assigned-clock-rates = <500000000>, <200000000>;
no-reset-control;
power-domains = <&mediamix_pd>;
status = "disabled";
cap_device {
compatible = "imx-isi-capture";
status = "disabled";
};
};
isp_0: isp@32e10000 {
compatible = "fsl,imx8mp-isp";
reg = <0x32e10000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
clock-names = "isp_root";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
power-domains = <&ispdwp_pd>;
status = "disabled";
};
isp_1: isp@32e20000 {
compatible = "fsl,imx8mp-isp";
reg = <0x32e20000 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
clock-names = "isp_root";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
power-domains = <&ispdwp_pd>;
status = "disabled";
};
mipi_csi_0: csi@32e40000 {
compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "disp_axi", "disp_apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
bus-width = <4>;
csi-gpr = <&mediamix_gasket0>;
csi-gpr2 = <&mediamix_gpr>;
gpr = <&mediamix_blk_ctl>;
no-reset-control;
power-domains = <&mipi_phy1_pd>;
status = "disabled";
};
mipi_csi_1: csi@32e50000 {
compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
reg = <0x32e50000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "disp_axi", "disp_apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <266000000>;
bus-width = <4>;
csi-gpr = <&mediamix_gasket1>;
csi-gpr2 = <&mediamix_gpr>;
gpr = <&mediamix_blk_ctl>;
no-reset-control;
power-domains = <&mipi_phy2_pd>;
status = "disabled";
};
};
};
};
pcie_phy: pcie-phy@32f00000 {
compatible = "fsl,imx8mp-pcie-phy";
reg = <0x0 0x32f00000 0x0 0x10000>;
clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
#phy-cells = <0>;
status = "disabled";
};
hsio_mix: hsio-mix@32f10000 {
compatible = "fsl,imx8mp-hsio-mix";
reg = <0x0 0x32f10000 0x0 0x8>;
};
dma_apbh: dma-apbh@33000000 {
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0 0x33000000 0 0x2000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
};
gpmi: gpmi-nand@33002000{
compatible = "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bch";
clocks = <&clk IMX8MP_CLK_NAND_ROOT>,
<&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
clock-names = "gpmi_io", "gpmi_bch_apb";
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
status = "disabled";
};
pcie: pcie@33800000 {
compatible = "fsl,imx8mp-pcie", "snps,dw-pcie";
reg = <0x0 0x33800000 0x0 0x400000>,
<0x0 0x1ff00000 0x0 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
interrupt-names = "msi", "dma";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
power-domains = <&pcie_pd>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIEPHY_PERST>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
fsl,imx8mp-hsio-mix = <&hsio_mix>;
status = "disabled";
};
pcie_ep: pcie_ep@33800000 {
compatible = "fsl,imx8mp-pcie-ep";
reg = <0x0 0x33800000 0x0 0x000400000>,
<0x0 0x18000000 0x0 0x08000000>;
reg-names = "regs", "addr_space";
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
interrupt-names = "dma";
fsl,max-link-speed = <3>;
power-domains = <&pcie_pd>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIEPHY_PERST>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
fsl,imx8mp-hsio-mix = <&hsio_mix>;
num-ib-windows = <4>;
num-ob-windows = <4>;
status = "disabled";
};
gpu_3d: gpu3d@38000000 {
compatible = "fsl,imx8-gpu";
reg = <0x0 0x38000000 0x0 0x8000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
<&clk IMX8MP_CLK_GPU3D_SHADER_DIV>,
<&clk IMX8MP_CLK_GPU_AXI>,
<&clk IMX8MP_CLK_GPU_AHB>;
clock-names = "core", "shader", "axi", "ahb";
assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE_SRC>,
<&clk IMX8MP_CLK_GPU3D_SHADER_SRC>,
<&clk IMX8MP_CLK_GPU_AXI>,
<&clk IMX8MP_CLK_GPU_AHB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <1000000000>, <1000000000>,
<800000000>, <400000000>;
power-domains = <&gpu3d_pd>;
status = "disabled";
};
gpu_2d: gpu2d@38008000 {
compatible = "fsl,imx8-gpu";
reg = <0x0 0x38008000 0x0 0x8000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
<&clk IMX8MP_CLK_GPU_AXI>,
<&clk IMX8MP_CLK_GPU_AHB>;
clock-names = "core", "axi", "ahb";
assigned-clocks = <&clk IMX8MP_CLK_GPU2D_SRC>,
<&clk IMX8MP_CLK_GPU_AXI>,
<&clk IMX8MP_CLK_GPU_AHB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <1000000000>, <800000000>, <400000000>;
power-domains = <&gpu2d_pd>;
status = "disabled";
};
usb3_phy0: usb-phy@381f0040 {
compatible = "fsl,imx8mp-usb-phy";
reg = <0 0x381f0040 0 0x40>;
clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
#phy-cells = <0>;
status = "disabled";
};
usb3_0: usb@32f10100 {
compatible = "fsl,imx8mp-dwc3";
reg = <0 0x32f10100 0 0x8>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI_DIV>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "bus", "suspend";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsiomix_pd>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_dwc3_0: dwc3@38100000 {
compatible = "snps,dwc3";
reg = <0 0x38100000 0 0x10000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
xhci-no-64bit-support;
usb3-resume-missing-cas;
snps,dis-u2-freeclk-exists-quirk;
snps,soft-itp-sync;
status = "disabled";
};
};
usb3_phy1: usb-phy@382f0040 {
compatible = "fsl,imx8mp-usb-phy";
reg = <0 0x382f0040 0 0x40>;
clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
#phy-cells = <0>;
status = "disabled";
};
usb3_1: usb@32f10108 {
compatible = "fsl,imx8mp-dwc3";
reg = <0 0x32f10108 0 0x8>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI_DIV>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "bus", "suspend";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsiomix_pd>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_dwc3_1: dwc3@38200000 {
compatible = "snps,dwc3";
reg = <0 0x38200000 0 0x10000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
xhci-no-64bit-support;
usb3-resume-missing-cas;
snps,dis-u2-freeclk-exists-quirk;
snps,soft-itp-sync;
status = "disabled";
};
};
vpu_g1: vpu_g1@38300000 {
compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro";
reg = <0x0 0x38300000 0x0 0x100000>;
reg-names = "regs_hantro";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_hantro";
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>;
clock-names = "clk_hantro", "clk_hantro_bus";
assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>, <&clk IMX8MP_CLK_VPU_BUS>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-rates = <600000000>, <600000000>;
power-domains = <&vpu_g1_pd>;
status = "disabled";
};
vpu_g2: vpu_g2@38310000 {
compatible = "nxp,imx8mm-hantro","nxp,imx8mp-hantro";
reg = <0x0 0x38310000 0x0 0x100000>;
reg-names = "regs_hantro";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_hantro";
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>;
clock-names = "clk_hantro", "clk_hantro_bus";
assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_CLK_VPU_BUS>;
assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-rates = <400000000>, <600000000>;
power-domains = <&vpu_g2_pd>;
status = "disabled";
};
vpu_vc8000e: vpu_vc8000e@38320000 {
compatible = "nxp,imx8mp-hantro-vc8000e";
reg = <0x0 0x38320000 0x0 0x10000>;
reg-names = "regs_hantro_vc8000e";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_hantro_vc8000e";
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>, <&clk IMX8MP_CLK_VPU_ROOT>;
clock-names = "clk_hantro_vc8000e", "clk_hantro_vc8000e_bus";
assigned-clocks = <&clk IMX8MP_CLK_VPU_VC8000E>,<&clk IMX8MP_CLK_VPU_BUS>;
assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>, <&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-rates = <400000000>, <600000000>;
power-domains = <&vpu_h1_pd>;
status = "disabled";
};
ml_vipsi: vipsi@38500000 {
compatible = "fsl,imx8-gpu", "fsl,imx8-vipsi";
reg = <0x0 0x38500000 0x0 0x20000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
<&clk IMX8MP_CLK_NPU_ROOT>,
<&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>;
clock-names = "core", "shader", "axi", "ahb";
assigned-clocks = <&clk IMX8MP_CLK_ML_SRC>,
<&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <1000000000>, <800000000>, <400000000>;
power-domains = <&mlmix_pd>;
status = "disabled";
};
dsp: dsp@3b6e8000 {
compatible = "fsl,imx8mp-dsp-v1";
memory-region = <&dsp_reserved>;
reg = <0x0 0x3B6E8000 0x0 0x88000>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_MU2_ROOT>;
clock-names = "ocram", "core", "debug", "mu2";
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
power-domains = <&audiomix_pd>;
mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
mboxes = <&mu2 2 0>,
<&mu2 2 1>,
<&mu2 3 0>,
<&mu2 3 1>;
status = "disabled";
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&lcdif1_disp>,
<&lcdif2_disp>,
<&lcdif3_disp>;
};
imx_ion: imx_ion {
compatible = "fsl,mxc-ion";
fsl,heap-id = <0>;
};
mix_gpu_ml: mix_gpu_ml {
compatible = "fsl,imx8mp-gpu", "fsl,imx8-gpu-ss";
cores = <&gpu_3d>, <&ml_vipsi>, <&gpu_2d>;
reg = <0x0 0x40000000 0x0 0xC0000000>, <0x0 0x0 0x0 0x10000000>;
reg-names = "phys_baseaddr", "contiguous_mem";
status = "disabled";
};
rpmsg: rpmsg{
compatible = "fsl,imx8mq-rpmsg";
/* up to now, the following channels are used in imx rpmsg
* - tx1/rx1: messages channel.
* - general interrupt1: remote proc finish re-init rpmsg stack
* when A core is partition reset.
*/
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
status = "disabled";
};
i2c_rpbus_3: i2c-rpbus-3 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
etm0: etm@28440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x28440000 0x0 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_0>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
};
etm1: etm@28540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x28540000 0x0 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_1>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
};
};
};
};
etm2: etm@28640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x28640000 0x0 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_2>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
etm2_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port2>;
};
};
};
};
etm3: etm@28740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x28740000 0x0 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A53_3>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
etm3_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port3>;
};
};
};
};
funnel0: funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
status = "disabled";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
remote-endpoint = <&etm1_out_port>;
};
};
port@2 {
reg = <2>;
ca_funnel_in_port2: endpoint {
remote-endpoint = <&etm2_out_port>;
};
};
port@3 {
reg = <3>;
ca_funnel_in_port3: endpoint {
remote-endpoint = <&etm3_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
funnel1: funnel@28c03000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x28c03000 0x0 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
remote-endpoint = <&ca_funnel_out_port0>;
};
};
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
/* M7 input */
};
};
port@2 {
reg = <2>;
hugo_funnel_in_port2: endpoint {
/* DSP input */
};
};
/* the other input ports are not connect to anything */
};
out-ports {
port {
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
};
};
etf@28c04000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x28c04000 0x0 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
port {
etf_in_port: endpoint {
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
};
out-ports {
port {
etf_out_port: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
};
etr@28c06000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x28c06000 0x0 0x1000>;
clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&etf_out_port>;
};
};
};
};
};
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