The DTS is for i.MX8MP DSP offload audio playback. DSP only use OCRAM
and OCRAM_A when audio playback, so DRAM can enter retention mode to
save Power. As the size limitation of OCRAM and OCRAM_A and the size
audio decoder library, the LPA playback only can support MP3 and AAC.
OCRAM address is 0x900000-0x990000. ATF will use 0x960000-0x980000.
DSP LPA will use ocram(0x900000-0x960000) and ocram_e(0x980000-
0x990000)
Signed-off-by: Bing Song <bing.song@nxp.com>
Verify the PCIe PLL_SYS reference clock source on EVK board.
The external OSC clock is used as PCIe REF clock source in default.
NOTE: Change the ext_osc of pcie/pcie_phy to '0' when enable SYS_PLL
clock mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Add the PCIe EP mode on iMX8MQ/MM/MP platforms.
And enable the EP mode on EVK boards.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Add "fsl,imx8mm-ocotp" as fallback compatible of i.MX8MP ocotp
to support SoC UID read.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
The interrupt parent of PMU node should be gic, so correct it to fix the pmu
no sampling/overflow interrupt issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The LCDIF3 is included in the HDMIMIX block, so it is
necessary to enable hdmimix power domain for LCDIF3 to
avoid any potential hang issue.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Since snvs clock runtime management added for snvs_rtc, all snvs_pwrkey
should also added snvs clock, otherwise, snvs clock will be off after
snvs-rct driver suspend and snvs_pwrkey interrupt may come after that,
hence, kernel will hang.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT gate controls
SAI PLL bus clock - it must be enabled if SAI PLL
programming is required.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This property will block the SS phy enter P3 when link at U3,
so remove it.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
This patch adds power domain property for ldb phy node, so that
the phy driver can enable runtime PM support.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
add compatible string "fsl,imx8-vipsi" to identify the vip core
for PM Qos
Signed-off-by: minjie.zhuang@nxp.com
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Integrate local HDMI display into EVK DTB to support the
DSI + LVDS + HDMI triple display, and previous single
display support for DSI, LVDS or HDMI is also remained.
Put LCDIF3 port to the same display-subsystem node as
LCDIF1 and LCDIF2 to realize this kind of triple display.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Integrate LVDS bridge with single channel display into EVK DTB
to support DSI + LVDS dual display, and the previous single
display support for DSI or LVDS is also remained. Put LCDIF1
and LCDIF2 ports into one display-subystem node to implement
this kind of dual display.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
As other devices in mediamix domain have already enabled
power domains, LDB is also required to enable the power
domains.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The mediamix block control module access requires the
'IMX8MP_CLK_MEDIA_APB_ROOT' clock to be enabled, so
add this clock to this device node.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
To align with the port names of 'lcdif2_disp' and 'lcdif3_disp',
rename 'lcdif_disp0' to 'lcdif1_disp'.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Since the 'mipi_phy1_ref' clock rate is usually set to
be 27MHz and won't be changed after boot up. So assign
27MHz rate instead of 594MHz to this clock is much more
reasonable.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The 'disp1_pix' clock is used to provide pixel clock for
LCDIF1 and its rate is closely related with the display
mode resolution which is configured. So this clock rate
is dynamically determined and unnecessary to be assigned
with a default value at boot up.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The 'video_pll1' clock is shared by MIPI and LVDS displays
and each of the display has a specific requirement for the
PLL rate which can be satified by set 'video_pll1' rate to
be 2079MHz. So assign 2079MHz rate to 'video_pll1' under
CCM device.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Move mipi_csi clock changes from imx8mp.dtsi into 0v2775 dtb,
to avoid failures for ov5460.
Tested with VSI ISP demo 28/02/20 release.
Not tested with camera on CSI2.
Fixes: 636de0a39e ("Add ov2775 dtb for imx8mp")
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Acked-by: G.n. Zhou <guoniu.zhou@nxp.com>
Add the PCIe power domain into the PCIe DTS node refer to the power
consumption refine.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-and-tested-by: Jacky Bai <ping.bai@nxp.com>
Make sure all the needed clocks are enabled for mipi_csi,
do not rely on mipi_dsi or lcdif to enable them.
Needed: media_cam1_pix, media_axi_root, media_apb_root
Tested with VSI ISP demo.
Not tested with camera on CSI2.
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Tested-by: Oliver Brown <oliver.brown@nxp.com>
Currently hsio root clock is always on, which should be handled
by hsiomix power domain driver but there is problem on doing that,
see commit 5aaceda10a ("MLK-23671-02 arm64: dts: imx8mp: Add the
rpm-always-on flag for hsiomix domain"):
"The hsiomix power domain need to be runtime always-on to maintain USB's
wakeup ability. As this domain need to be boot on by default, no one
will call the power on callback during system boot up, the clock
enable/disable will mismatch, so remove the clocks from this domain.
the necessary clocks will be handled in TF-A."
There is one clock(AXI_DIV) shared between hsiomix and USB, with
rpm-always-on property added, like above commit description, power
domain driver will not do enable/disable and think it's always on, but
it can be disabled by USB driver, afterwards if power domain driver does
hsiomix register access, system will hang because the required clock was
disabled.
Now with above commit and change in TF-A, those clocks are not
controlled by Linux for power domain operations, but user driver(i.e. USB
and PCIE) has to handle it.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
USB controller isolation is controlled by hsiomix power domain,
instead of usb_otg1_pd and usb_otg2_pd, those 2 power domains are
for USB PHY isolation and in our case, PHY is power is kept always
on(but can be suspended).
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
1. add i2c-rpmsg support for i2c3
2. reserve memory for LPA, for the accessable memory
of m7: 0x40000000-0xbfffffff.
3. support LPA, playback only
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
the HDMI APB clock & 266M REF clock should be on when doing HDMIMIX power domain
on/off, so add these clock to hdmimix pd node.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
There is hardware issue: TKT0535653
SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1
The workaround is:
As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
we just need to keep it on as reset state, don't touch it
in kernel, then every thing is same as before.
So for sdma node, it only need to care about AHB and IPG clock,
the gate of AUDIOMIX_CLKEN0[SDMA2] is always enabled.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
The hsiomix power domain need to be runtime always-on to maintain USB's
wakeup ability. As this domain need to be boot on by default, no one will
call the power on callback during system boot up, the clock enable/disable
will mismatch, so remove the clocks from this domain. the necessary clocks
will be handled in TF-A.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add the PCIe DMA IRQ name.
Enable the PCIe EP RC validation on iMX8MP EVK boards.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
This patch adds APB clock related properties in lvds phy node,
so that the driver may get and control the APB clock.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The HSIOMIX domain need to be on if usb wakeup is enabled for system
wakeup source, so add the 'active-wakeup' property for this domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add power domain property for vpu node to enable power domain
off when module entering runtime PM.
BuildInfo:
- ATF 13de44f73
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
SOFITPSYNC
If this bit is set to '0' operating in host mode, the core keeps the
UTMI/ULPI PHY on the first port in a non-suspended state whenever there
is a SuperSpeed port that is not in Rx.Detect, SS.Disable and U3.
If this bit is set to '1' operating in host mode, the core keeps the
UTMI/ULPI PHY on the first port in a non-suspended state whenever the
other non-SuperSpeed ports are not in a suspended state. This feature is
useful because it saves power by suspending UTMI/ULPI when SuperSpeed
only is active, and it helps resolve when the PHY does not transmit a
host resume unless it is placed in suspend state. This bit must be
programmed as a part of initialization at power-on reset, and must not
be dynamically changed afterwards.
with this property specified, this bit is set to be 1.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
IP module name is AUDIO XCVR, eARC being just one
of the audio interfaces supported by XCVR IP module.
Use IP module name instead of a specific audio interface
in order to avoid confusion.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
There is a shared gate clock exists after 'IMX8MP_CLK_MEDIA_
AXI_ROOT' and 'IMX8MP_CLK_MEDIA_AXI_ROOT' clocks according to
the clock tree, so correct clock values for 'mediamix-pd' by
using the corresponding gate clocks.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
The GPU3D shader clock must be on to make sure that GPU3D can be reset
successfully.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
With the reserved memory for optee, Linux is no
longer able to allocate CMA within the allocation
range defined in the dtb.
Increase the alloc-range so that Linux can allocate in the 4G
address range (in case some DMA are not able to address more).
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
Correct the HDMI irqsteer's interrupt controller parent, otherwise the HDMI
irq can NOT wakeup the cpu core from idle timely, then HDMI performance
will be impacted.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add new compatible 'imx8mp-sdma' for sdma2/sdma3 to support resume back after
audiomix off.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The GPU AXI/AHB & ML AXI/AHB clock must be on when doing corresponding
power domain on/off, so Add these clocks to GPUMIX & MLMIX power domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
With GPC as interrupt parent, need set edac and irqsteer interrupt
parent as gpc.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
BL32 base address is set within the first 1GByte of DDR.
As a new rule it will be set at base address + 0x16000000.
This new position will relax current dependency of the OPTEE
base address on the size of the DDR.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Design team confirms that i.MX8MP can support ARM/SOC with any
combinations(SOD/OD, SOD/ND, OD/OD, OD/ND, ND/ND, ND/OD), it has
level shift and STA timing passed, so ARM's 1.2GHz opp can use
typical 0.85V directly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Bing Song