![Venkateswara Rao Mandela](/assets/img/avatar_default.png)
Description of DRA7 Errata i932: In rare circumstances DPLL_VIDEO1 and DPLL_VIDEO2 PLL's may not lock on the first attempt during DSS initialization. When this occurs, a subsequent attempt to relock the PLL will result in PLL successfully locking. This patch does the following as per the errata recommendation: - retries locking the PLL upto 20 times. - The time to wait for a PLL lock set to 1000 REFCLK cycles. We use usleep_range to wait for 1000 REFCLK cycles in the us range. This tight constraint is imposed as a lock later than 1000 REFCLK cycles may have high jitter. - Criteria for PLL lock is extended from check on just the PLL_LOCK bit to check on 6 PLL_STATUS bits. Silicon Versions Impacted: DRA71, DRA72, DRA74, DRA76 - All silicon revisions AM57x - All silicon revisions OMAP4/5 are not impacted by this errata Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com> [tomi.valkeinen@ti.com: ported to v4.14] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
206 lines
4.5 KiB
C
206 lines
4.5 KiB
C
/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include "omapdss.h"
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#include "dss.h"
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struct dss_video_pll {
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struct dss_pll pll;
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struct device *dev;
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void __iomem *clkctrl_base;
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};
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#define REG_MOD(reg, val, start, end) \
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writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
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static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
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{
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REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
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}
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static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
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{
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REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
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}
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static void dss_dpll_power_enable(struct dss_video_pll *vpll)
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{
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REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
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/*
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* DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
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* so we have to use fixed delay here.
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*/
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msleep(1);
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}
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static void dss_dpll_power_disable(struct dss_video_pll *vpll)
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{
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REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
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}
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static int dss_video_pll_enable(struct dss_pll *pll)
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{
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struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
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int r;
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r = dss_runtime_get(pll->dss);
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if (r)
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return r;
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dss_ctrl_pll_enable(pll, true);
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dss_dpll_enable_scp_clk(vpll);
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r = dss_pll_wait_reset_done(pll);
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if (r)
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goto err_reset;
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dss_dpll_power_enable(vpll);
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return 0;
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err_reset:
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dss_dpll_disable_scp_clk(vpll);
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dss_ctrl_pll_enable(pll, false);
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dss_runtime_put(pll->dss);
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return r;
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}
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static void dss_video_pll_disable(struct dss_pll *pll)
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{
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struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
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dss_dpll_power_disable(vpll);
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dss_dpll_disable_scp_clk(vpll);
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dss_ctrl_pll_enable(pll, false);
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dss_runtime_put(pll->dss);
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}
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static const struct dss_pll_ops dss_pll_ops = {
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.enable = dss_video_pll_enable,
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.disable = dss_video_pll_disable,
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.set_config = dss_pll_write_config_type_a,
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};
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static const struct dss_pll_hw dss_dra7_video_pll_hw = {
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.type = DSS_PLL_TYPE_A,
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.n_max = (1 << 8) - 1,
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.m_max = (1 << 12) - 1,
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.mX_max = (1 << 5) - 1,
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.fint_min = 500000,
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.fint_max = 2500000,
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.clkdco_max = 1800000000,
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.n_msb = 8,
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.n_lsb = 1,
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.m_msb = 20,
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.m_lsb = 9,
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.mX_msb[0] = 25,
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.mX_lsb[0] = 21,
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.mX_msb[1] = 30,
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.mX_lsb[1] = 26,
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.mX_msb[2] = 4,
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.mX_lsb[2] = 0,
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.mX_msb[3] = 9,
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.mX_lsb[3] = 5,
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.has_refsel = true,
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.errata_i886 = true,
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.errata_i932 = true,
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};
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struct dss_pll *dss_video_pll_init(struct dss_device *dss,
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struct platform_device *pdev, int id,
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struct regulator *regulator)
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{
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const char * const reg_name[] = { "pll1", "pll2" };
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const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
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const char * const clkin_name[] = { "video1_clk", "video2_clk" };
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struct resource *res;
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struct dss_video_pll *vpll;
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void __iomem *pll_base, *clkctrl_base;
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struct clk *clk;
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struct dss_pll *pll;
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int r;
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/* PLL CONTROL */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]);
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pll_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pll_base))
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return ERR_CAST(pll_base);
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/* CLOCK CONTROL */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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clkctrl_name[id]);
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clkctrl_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(clkctrl_base))
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return ERR_CAST(clkctrl_base);
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/* CLKIN */
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clk = devm_clk_get(&pdev->dev, clkin_name[id]);
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if (IS_ERR(clk)) {
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DSSERR("can't get video pll clkin\n");
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return ERR_CAST(clk);
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}
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vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
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if (!vpll)
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return ERR_PTR(-ENOMEM);
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vpll->dev = &pdev->dev;
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vpll->clkctrl_base = clkctrl_base;
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pll = &vpll->pll;
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pll->name = id == 0 ? "video0" : "video1";
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pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
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pll->clkin = clk;
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pll->regulator = regulator;
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pll->base = pll_base;
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pll->hw = &dss_dra7_video_pll_hw;
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pll->ops = &dss_pll_ops;
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r = dss_pll_register(dss, pll);
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if (r)
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return ERR_PTR(r);
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return pll;
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}
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void dss_video_pll_uninit(struct dss_pll *pll)
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{
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dss_pll_unregister(pll);
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}
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