178e9fc47a
This patch provide a basic PMU, riscv_base_pmu, which supports two general hardware event, instructions and cycles. Furthermore, this PMU serves as a reference implementation to ease the portings in the future. riscv_base_pmu should be able to run on any RISC-V machine that conforms to the Priv-Spec. Note that the latest qemu model hasn't fully support a proper behavior of Priv-Spec 1.10 yet, but work around should be easy with very small fixes. Please check https://github.com/riscv/riscv-qemu/pull/115 for future updates. Cc: Nick Hu <nickhu@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Signed-off-by: Alan Kao <alankao@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
45 lines
839 B
Makefile
45 lines
839 B
Makefile
#
|
|
# Makefile for the RISC-V Linux kernel
|
|
#
|
|
|
|
ifdef CONFIG_FTRACE
|
|
CFLAGS_REMOVE_ftrace.o = -pg
|
|
CFLAGS_REMOVE_setup.o = -pg
|
|
endif
|
|
|
|
extra-y += head.o
|
|
extra-y += vmlinux.lds
|
|
|
|
obj-y += cpu.o
|
|
obj-y += cpufeature.o
|
|
obj-y += entry.o
|
|
obj-y += irq.o
|
|
obj-y += process.o
|
|
obj-y += ptrace.o
|
|
obj-y += reset.o
|
|
obj-y += setup.o
|
|
obj-y += signal.o
|
|
obj-y += syscall_table.o
|
|
obj-y += sys_riscv.o
|
|
obj-y += time.o
|
|
obj-y += traps.o
|
|
obj-y += riscv_ksyms.o
|
|
obj-y += stacktrace.o
|
|
obj-y += vdso.o
|
|
obj-y += cacheinfo.o
|
|
obj-y += vdso/
|
|
|
|
CFLAGS_setup.o := -mcmodel=medany
|
|
|
|
obj-$(CONFIG_SMP) += smpboot.o
|
|
obj-$(CONFIG_SMP) += smp.o
|
|
obj-$(CONFIG_MODULES) += module.o
|
|
obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
|
|
|
|
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
|
|
obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
|
|
|
|
obj-$(CONFIG_PERF_EVENTS) += perf_event.o
|
|
|
|
clean:
|