64adb6bb62
The current ar724x_pci_{read,write} functions are
broken. Due to that, pci_read_config_byte returns
with bogus values, and pci_write_config_{byte,word}
unconditionally clears the accessed PCI configuration
registers instead of changing the value of them.
The patch fixes the broken functions, thus the PCI
configuration space can be accessed correctly.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3493/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
144 lines
3 KiB
C
144 lines
3 KiB
C
/*
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* Atheros 724x PCI support
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*
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* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <asm/mach-ath79/pci.h>
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#define AR724X_PCI_CFG_BASE 0x14000000
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#define AR724X_PCI_CFG_SIZE 0x1000
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#define AR724X_PCI_MEM_BASE 0x10000000
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#define AR724X_PCI_MEM_SIZE 0x08000000
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static DEFINE_SPINLOCK(ar724x_pci_lock);
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static void __iomem *ar724x_pci_devcfg_base;
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static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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unsigned long flags;
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void __iomem *base;
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u32 data;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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base = ar724x_pci_devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xff;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xffff;
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break;
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case 4:
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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*value = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t value)
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{
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unsigned long flags;
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void __iomem *base;
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u32 data;
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int s;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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base = ar724x_pci_devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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s = ((where & 3) * 8);
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data &= ~(0xff << s);
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data |= ((value & 0xff) << s);
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break;
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case 2:
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s = ((where & 2) * 8);
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data &= ~(0xffff << s);
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data |= ((value & 0xffff) << s);
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break;
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case 4:
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data = value;
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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__raw_writel(data, base + (where & ~3));
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/* flush write */
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__raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops ar724x_pci_ops = {
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.read = ar724x_pci_read,
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.write = ar724x_pci_write,
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};
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static struct resource ar724x_io_resource = {
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.name = "PCI IO space",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IO,
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};
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static struct resource ar724x_mem_resource = {
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.name = "PCI memory space",
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.start = AR724X_PCI_MEM_BASE,
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.end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct pci_controller ar724x_pci_controller = {
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.pci_ops = &ar724x_pci_ops,
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.io_resource = &ar724x_io_resource,
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.mem_resource = &ar724x_mem_resource,
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};
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int __init ar724x_pcibios_init(void)
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{
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ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
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AR724X_PCI_CFG_SIZE);
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if (ar724x_pci_devcfg_base == NULL)
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return -ENOMEM;
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register_pci_controller(&ar724x_pci_controller);
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return PCIBIOS_SUCCESSFUL;
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}
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