Guo Ren 8d11f21a73 csky: Fixup barrier design ... Remove shareable bit for ordering barrier, just keep ordering in current hart is enough for SMP. Using three continuous sync.is as PTW barrier to prevent speculative PTW in 860 microarchitecture. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>		2021-01-12 09:52:40 +08:00
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abiv1	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
abiv2	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
boot	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
configs	csky: Minimize defconfig to support buildroot config.fragment	2020-02-21 15:43:25 +08:00
include	csky: Fixup barrier design	2021-01-12 09:52:40 +08:00
kernel	csky: Fixup show_regs doesn't contain regs->usp	2021-01-12 09:52:40 +08:00
lib	csky: Add support for function error injection	2020-07-31 01:52:07 +00:00
mm	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
Kconfig	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
Kconfig.debug	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
Kconfig.platforms	csky/Kconfig: Add Kconfig.platforms to support some drivers	2020-02-21 15:43:24 +08:00
Makefile	csky: Fixup calltrace panic	2020-05-13 17:55:06 +08:00