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alistair23-linux/arch/csky/abiv2
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Guo Ren 0c8a32eed1 csky: Add memory layout 2.5G(user):1.5G(kernel) 
There are two ways for translating va to pa for csky:
 - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
 - Use SSEG0/1 (Simple Segment Mapping)

We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2021-01-12 09:52:40 +08:00
..
inc/abi csky: Add memory layout 2.5G(user):1.5G(kernel) 2021-01-12 09:52:40 +08:00
cacheflush.c csky: Add flush_icache_mm to defer flush icache all 2020-02-21 15:43:24 +08:00
fpu.c csky: Fixup init_fpu compile warning with __init 2020-03-08 20:55:14 +08:00
Makefile treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21 10:50:46 +02:00
mcount.S csky: Fixup kprobes handler couldn't change pc 2020-07-31 01:51:57 +00:00
memcmp.S csky: Library functions 2018-10-26 00:54:24 +08:00
memcpy.S csky: fixup remove vdsp implement for kernel. 2018-12-31 22:56:59 +08:00
memmove.S csky: Fixup vdsp&fpu issues in kernel 2019-04-22 13:44:57 +08:00
memset.S csky: Library functions 2018-10-26 00:54:24 +08:00
strcmp.S csky: Library functions 2018-10-26 00:54:24 +08:00
strcpy.S csky: Library functions 2018-10-26 00:54:24 +08:00
strksyms.c csky: Library functions 2018-10-26 00:54:24 +08:00
strlen.S csky: Library functions 2018-10-26 00:54:24 +08:00
sysdep.h csky: Library functions 2018-10-26 00:54:24 +08:00